View MAX14830ETM_7984176.PDF datasheet online --- IC-ON-LINE

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_______________________________________________________________ maxim integrated products 1 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com. max14830 quad serial uart with 128-word fifos and internal oscillator 19-5547; rev 0; 9/10 general description the max14830 is an advanced quad universal asyn - chronous receiver-transmitter (uart), each uart hav - ing 128 words of receive and transmit first-in/first-out (fifo) and a high-speed serial peripheral interface (spik ) or i 2 c controller interface. a pll and fractional baud-rate generators allow a high degree of flexibility in baud-rate programming and reference clock selection. each of the four uarts is selected by in-band spi/i 2 c addressing. logic-level translation on the transceiver and controller interfaces allows ease of interfacing to microcontrollers, fpgas, and transceivers that are pow - ered by differing supply voltages. extensive features simplify transceiver control in half- duplex communication applications. the max14830 features the ability to synchronize the start of individual uarts transmission by spi-based triggering. on-board timers allow programming of delays between transmit - ters as well as clock generation on gpios. the 128-word fifos have advanced fifo control reduc - ing host processor data flow management. the max14830 is available in a 48-pin tqfn (7mm x 7mm) package and is specified to operate over the extended -40 n c to +85n c temperature range. applications industrial control systems programmable logic controllers (plc) io-link master controllers automotive infotainment systems medical systems point-of-sales systems airplane communication buses features s spi up to 26mhz clock rate s fast-mode plus (fm+) i 2 c interface up to 1mhz s 128-word transmit and receive fifos per uart s 6mbaud (max) data rate in 16x sampling mode s 12/24mbaud (max) data rate in 2x/4x rate modes s integrated internal oscillator, external crystal, or clock functionality s fractional baud-rate generators, predivider, and phase-locked loop (pll) s transmitter synchronization through spi commands s four timers routed to gpios s automatic hardware flow control using rts_ and cts_ outputs and inputs s automatic software flow control (xon/xoff) s auto transceiver direction control s programmable setup and hold times for transceiver control s auto transmitter disable s half-duplex echo suppression s special character detection s 9-bit multidrop mode address detection and filtering s sir- and mir-compliant irda sm encoder/ decoders s 16 flexible gpios with 20ma drive capability s +2.35v to +3.6v supply range s logic-level translation down to 1.61v on controller and transceiver interfaces s small tqfn (7mm x 7mm) package ordering information + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. spi is a trademark of motorola, inc. irda is a registered service mark of infrared data association corporation. typical operating circuits appear at end of data sheet. part temp range pin-package MAX14830ETM+ -40nc to +85nc 48 tqfn-ep*
max14830 quad serial uart with 128-word fifos and internal oscillator 2 table of con tents general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 package thermal characteristics (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 test circuits/timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 receive and transmit fifos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 transmitter operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 receiver operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 line noise indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 clocking and baud-rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 internal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 pll and predivider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 fractional baud-rate generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2x and 4x rate modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 low-frequency timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 uart clock to gpio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 multidrop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 auto data filtering in multidrop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 auto transceiver direction control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 transmitter triggering and synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 transmitter synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 intrachip and interchip synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 delayed triggering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 trigger accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 synchronization accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 auto transmitter disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
max14830 quad serial uart with 128-word fifos and internal oscillator 3 echo suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 auto hardware flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 autorts control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 autocts control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 fifo interrupt triggering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 auto software (xon/xoff) flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 transmitter control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 receiver overflow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 power-up and irq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 interrupt structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 interrupt enabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 interrupt clearing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 detailed register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 serial controller interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 spi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 miso operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 spi burst access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 fast read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 i 2 c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 start, stop, and repeated start conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 slave address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 single-byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 burst write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 single-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 burst read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 acknowledge bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 startup and initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 low-power operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 interrupts and polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 logic-level translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 io-link application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 typical operating circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 chip information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table of con tent s (continued)
max14830 quad serial uart with 128-word fifos and internal oscillator 4 list of figures figure 1. i 2 c timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 2. spi timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 3. transmit fifo signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 4. receive data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 5. receive fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 6. midbit sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 7. clock selection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 8. 2x and 4x baud rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 9. gpio_ clock pulse generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 10. auto transceiver direction control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 11. setup and hold times in auto transceiver direction control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 12. single transmitter trigger accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 13. multiple transmitter synchronization accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 14. echo suppression timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 15. half-duplex with echo suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 16. simplified interrupt structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 17. pll signal path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 18. spi write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 19. spi read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 20. spi fast read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 21. i 2 c start, stop and repeated start conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 22. write byte sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 23. burst write sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 24. read byte sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 25. burst read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 26. acknowledge bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 27. startup and initialization flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 28. logic-level translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 29. interchip synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
max14830 quad serial uart with 128-word fifos and internal oscillator 5 list of tables table 1. uart gpio assignments for gpio interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 2. stopbits truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 3. length_ truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 4. swflow_ truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 5. uart gpio assignments for gpio configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 6. uart gpio assignments for gpio input/output data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 7. pllfactor_ selector guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 8. globlcomnd command descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 9. extended mode addressing (spi only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 10. spi command byte configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 11. spi u1, u0 uart selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 12. i 2 c address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
max14830 quad serial uart with 128-word fifos and internal oscillator 6 list of registers rhrreceiver hold register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 thrtransmit hold register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 irqenirq enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 isrinterrupt status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 lsrintenline status interrupt enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 lsrline status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 spclchrintenspecial character interrupt enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 spclcharintspecial character interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 stsintensts interrupt enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 stsintstatus interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 mode1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 mode2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 lcrline control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 rxtimeoutreceiver timeout register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 hdplxdelay register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 irda register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 flowlvlflow level register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 fifotriglvlfifo interrupt trigger level register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 txfifolvltransmit fifo level register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 rxfifolvlreceive fifo level register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 flowctrlflow control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 xon1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 xon2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 xoff1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 xoff2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 gpioconfggpio configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 gpiodatagpio data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 pllconfigpll configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 brgconfigbaud-rate generator configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 divlsbbaud-rate generator lsb divisor register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 divmsbbaud-rate generator msb divisor register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 clksourceclock source register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 globalirqglobal irq register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 globlcomndglobal command register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 txsynchtransmitter synchronization register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 synchdelay1synchronization delay register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 synchdelay2synchronization delay register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 timer1timer register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 timer2timer register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 revidrevision identification register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
max14830 quad serial uart with 128-word fifos and internal oscillator 7 functional diagram registers and control tx0 rx0 gpio0 gpio3 uarto 4 cts0 rts0 tx1 rx1 gpio4 gpio7 uart1 cts1 rts1 tx2 rx2 gpio8 gpio11 uart2 cts2 rts2 spi and i 2 c interface ldo pll divider v l logic-level translation ldoen mosi/a1 miso/sda sclk/scl tx3 rx3 gpio12 gpio15 uart3 cts3 rts3 v a v ext v 18 transmitter sync logic-level translation crystal oscillator internal oscillator 4 fractional baud-rate generator spi/i 2 c cs/a0 rst irq xin xout dgnd agnd max14830
max14830 quad serial uart with 128-word fifos and internal oscillator 8 stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (voltages referenced to agnd.) v l , v a , v ext , xin ................................................ -0.3v to +4.0v v 18 , xout .................................................. -0.3v to (v a + 0.3v) rst, irq , mosi/a1, cs /a0, sclk/scl, miso/sda, ldoen, spi/ i2c .................. -0.3v to (v l + 0.3v) tx0, rx0, cts0 , gpio0, gpio1, gpio2, gpio3 ..................................... -0.3v to (v ext + 0.3v) tx1, rx1, cts1 , gpio4, gpio5, gpio6, gpio7 ..................................... -0.3v to (v ext + 0.3v) tx2, rx2, cts2 , gpio8, gpio9, gpio10, gpio11 ................................. -0.3v to (v ext + 0.3v) tx3, rx3, cts3 , gpio12, gpio13, gpio14, gpio15 ................................. -0.3v to (v ext + 0.3v) dgnd .................................................................. -0.3v to +0.3v continuous power dissipation (t a = +70 nc) 48-pin tqfn (derate 38.5mw/ n c above +70nc).....3076.9mw operating temperature range ........................ -40 n c to +85nc maximum junction temperature ................................. +150 nc storage temperature range ......................... -65 n c to +150nc lead temperature (soldering, 10s) .................................. 300nc soldering temperature (reflow) ..................................... +260nc dc e lectrical characteristics (v a = +2.35v to +3.6v, v l = +1.71v to +3.6v, v ext = +1.71v to +3.6v, t a = -40 n c to +85n c, unless otherwise noted. typical values are at v a = +2.5v, v l = +1.8v, v ext = +2.8v, t a = +25 n c.) (notes 2, 3) absolute maximum ratings note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four- layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. package thermal characteristics ( note 1) tqfn junction-to-ambient thermal resistance ( b ja ) ........... 26nc/w junction-to-case thermal resistance ( b jc ) .................. 1nc/w parameter symbol conditions min typ max units digital interface supply voltage v l 1.71 3.6 v analog supply voltage v a 2.35 3.6 v uart interface logic supply voltage v ext 1.71 3.6 v logic supply voltage v 18 1.65 1.95 v current consumption v a supply current i a 1.8mhz crystal oscillator active, pll dis - abled, spi/i 2 c interface idle, uart inter - faces idle, v ldoen = v l 400 fa baud rate = 1mbps, 20mhz external clock, spi/i 2 c interface idle, pll disabled, all uarts in loopback mode, v ldoen = 0v 0.5 ma internal oscillator enabled, pll = 6x, spi/ i 2 c interface idle, baud rate = 115kbps, all uarts in loopback mode, v ldoen = 0v 5 v a shutdown supply current i ashdn shutdown mode, v ldoen = 0v, v rst = 0v, all inputs and outputs are idle 35 fa
max14830 quad serial uart with 128-word fifos and internal oscillator 9 dc e lectrical characteristics (continued) (v a = +2.35v to +3.6v, v l = +1.71v to +3.6v, v ext = +1.71v to +3.6v, t a = -40 n c to +85n c, unless otherwise noted. typical values are at v a = +2.5v, v l = +1.8v, v ext = +2.8v, t a = +25 n c.) (notes 2, 3) parameter symbol conditions min typ max units v l shutdown or sleep supply current i l shutdown mode, v ldoen = 0v, v rst = 0v, all inputs and outputs are idle 12 fa v ext shutdown supply current i ext shutdown mode, v ldoen = 0v, v rst = 0v, all inputs and outputs are idle 8 fa v 18 input power-supply current in shutdown mode i 18shdn shutdown mode, v ldoen = 0v, v rst = 0v, all inputs and outputs are idle 80 fa v 18 input power-supply current i 18 baud rate = 1mbps, 20mhz external clock, pll disabled, all uarts in loopback mode, v ldoen = 0v (note 4) 5 ma sclk/scl, miso/sda miso/sda output low voltage in i 2 c mode v ol,i2c i load = -3ma, v l > 2v 0.4 v i load = -3ma, v l < 2v 0.2 x v l miso/sda output low voltage in spi mode v ol,spi i load = -2ma 0.4 v miso/sda output high voltage in spi mode v oh,spi i load = 2ma v l - 0.4 v input low voltage v il spi and i 2 c mode 0.3 x v l v input high voltage v ih spi and i 2 c mode 0.7 x v l v input hysteresis v hyst spi and i 2 c mode 0.05 x v l v input leakage current i il v in = 0 to v l , spi and i 2 c mode -1 +1 fa input capacitance c in spi and i 2 c mode 5 pf spi/i2c, cs /a0, mosi/a1 inputs input low voltage v il spi and i 2 c mode 0.3 x v l v input high voltage v ih spi and i 2 c mode 0.7 x v l v input hysteresis v hyst spi and i 2 c mode 50 mv input leakage current i il v in = 0 to v l , spi and i 2 c mode -1 +1 fa input capacitance c in spi and i 2 c mode 5 pf irq output (open drain) output low voltage v ol i load = -2ma 0.4 v output leakage current i lk v irq = 0 to v l , irq is not asserted -1 +1 fa ldoen and rst inputs input low voltage v il 0.3 x v l v input high voltage v ih 0.7 x v l v input hysteresis v hyst 50 mv input leakage current i in v in = 0 to v l -1 +1 fa uart interface rts0, rts1, rts2, rts3, tx0, tx1, tx2, tx3 outputs output low voltage v ol i load = -2ma 0.4 v output high voltage v oh i load = 2ma v ext - 0.4 v input leakage current i in output is three-stated, v rts_ = 0 to v ext -1 +1 fa input capacitance c in high-z mode 5 pf
max14830 quad serial uart with 128-word fifos and internal oscillator 10 dc e lectrical characteristics (continued) (v a = +2.35v to +3.6v, v l = +1.71v to +3.6v, v ext = +1.71v to +3.6v, t a = -40 n c to +85n c, unless otherwise noted. typical values are at v a = +2.5v, v l = +1.8v, v ext = +2.8v, t a = +25 n c.) (notes 2, 3) ac e lectrical characteristics (v a = +2.35v to +3.6v, v l = +1.71v to +3.6v, v ext = +1.71v to +3.6v, t a = -40 n c to +85n c, unless otherwise noted. typical values are at v a = +2.8v, v l = +1.8v, v ext = +2.5v, t a = +25 n c.) (notes 2, 3) parameter symbol conditions min typ max units rx0, rx1, rx2, rx3, cts0, cts1, cts2, cts3 inputs input low voltage v il 0.3 x v ext v input high voltage v ih 0.7 x v ext v input hysteresis v hyst 50 mv cts0, cts1, cts2, cts3 input leakage current i in_cts v cts_ = 0 to v ext -1 +1 fa rx0, rx1, rx2, rx3 pullup current i in_rx_ v rx_ = 0v -7.5 -5.5 -3.5 fa input capacitance c in_uart 5 pf gpio0Cgpio15 inputs/outputs output low voltage v ol i load = -20ma, v ext > 2.3v, push-pull or open drain 0.45 v i load = -20ma, v ext < 2.3v, push-pull or open drain 0.55 output high voltage v oh i load = 5ma, push-pull v ext - 0.4 v input low voltage v il gpio_ is configured as an input 0.4 v input high voltage v ih gpio_ is configured as an input 2/3 x v ext v pulldown current i pd gpio_ = v ext 3.5 5.5 7.5 fa xin input low voltage v il 0.2 v input high voltage v ih 1.2 v input capacitance c xin 16 pf xout input capacitance c xout 16 pf parameter symbol conditions min typ max units internal oscillator internal oscillator frequency t a = 0 n c to +70nc -2% 614.4 +2% khz t a = -40 n c to +85nc -3% 614.4 +3% external crystal frequency f xosc 1 4 mhz external clock frequency f clk 0.5 35 mhz external clock duty cycle (note 5) 45 55 % baud-rate generator clock input f ref (note 5) 96 mhz
max14830 quad serial uart with 128-word fifos and internal oscillator 11 ac e lectrical characteristics (continued) (v a = +2.35v to +3.6v, v l = +1.71v to +3.6v, v ext = +1.71v to +3.6v, t a = -40 n c to +85n c, unless otherwise noted. typical values are at v a = +2.8v, v l = +1.8v, v ext = +2.5v, t a = +25 n c.) (notes 2, 3) parameter symbol conditions min typ max units i 2 c bus: timing characteristics (see figure 1) scl clock frequency f scl standard mode 100 khz fast mode 400 fast mode plus 1000 bus free time between a stop and start condition t buf standard mode 4.7 fs fast mode 1.3 fast mode plus 0.5 hold time for start condition and repeated start condition t hd:sta standard mode 4.0 fs fast mode 0.6 fast mode plus 0.26 low period of the scl clock t low standard mode 4.7 fs fast mode 1.3 fast mode plus 0.5 high period of the scl clock t high standard mode 4.0 fs fast mode 0.6 fast mode plus 0.26 data hold time t hd:dat standard mode 0 0.9 fs fast mode 0 0.9 fast mode plus 0 data setup time t su:dat standard mode 250 ns fast mode 100 fast mode plus 50 setup time for repeated start condition t su:sta standard mode 4.7 fs fast mode 0.6 fast mode plus 0.26 rise time of sda and scl signals receiving t r standard mode (0.3 x v l to 0.7 x v l ) (note 6) 20 + 0.1c b 1000 ns fast mode (0.3 x v l to 0.7 x v l ) (note 6) 20 + 0.1c b 300 fast mode plus 120 fall time of sda and scl signals t f standard mode (0.7 x v l to 0.3 x v l ) (note 6) 20 + 0.1c b 300 ns fast mode (0.7 x v l to 0.3 x v l ) (note 6) 20 + 0.1c b 300 fast mode plus 120 setup time for stop condition t su:sto standard mode 4.7 fs fast mode 0.6 fast mode plus 0.26 capacitive load for sda and scl (note 4) c b standard mode 400 pf fast mode 400 fast mode plus 550
max14830 quad serial uart with 128-word fifos and internal oscillator 12 ac e lectrical characteristics (continued) (v a = +2.35v to +3.6v, v l = +1.71v to +3.6v, v ext = +1.71v to +3.6v, t a = -40 n c to +85n c, unless otherwise noted. typical values are at v a = +2.8v, v l = +1.8v, v ext = +2.5v, t a = +25 n c.) (notes 2, 3) note 2: all devices are production tested at t a = +25 n c. specifications over temperature are guaranteed by design. note 3: currents entering the ic are negative, and currents exiting the ic are positive. note 4: when v 18 is powered by an external voltage regulator, the external power supply must have current capability above or equal to i 18 . note 5: not production tested. guaranteed by design. note 6: c b is the total capacitance of either the clock or data line of the synchronous bus in pf. parameter symbol conditions min typ max units scl and sda i/o capacitance c i/o (note 5) 10 pf pulse width of spike suppressed t sp 50 ns spi bus: timing characteristics (see figure 2) sclk clock period t ch+cl 38.4 ns sclk pulse width high t ch 16 ns sclk pulse width low t cl 16 ns cs fall to sclk rise time t css 0 ns mosi hold time t dh 3 ns mosi setup time t ds 5 ns output data propagation delay t do 20 ns miso rise and fall times t ft 10 ns cs hold time t csh 30 ns
max14830 quad serial uart with 128-word fifos and internal oscillator 13 test circuits/timing diagrams figure 1. i 2 c timing diagram figure 2. spi timing diagram sda start condition (s) start condition (s) repeated start condition (sr) stop condition (p) scl t hd:sta t su:dat t su:sta t hd:dat t hd:sta t su:sto t r t f t buf t high t low t r t f cs sclk mosi miso t css t cl t ds t dh t ch t do t csh
max14830 quad serial uart with 128-word fifos and internal oscillator 14 typical operating characteristics (t a = +25c, unless otherwise noted.) transmitter synchronization max14830 toc05 200s/div tx0 2v/div 138.46kbaud tx1 2v/div 19.23kbaud tx2 2v/div 9.615kbaud tx3 2v/div 6.41kbaud gpio_ output low voltage vs. sink current (push-pull) max14830 toc04 v ol (v) i sink (ma) 3 2 1 20 40 60 80 100 120 140 160 0 0 4 v ext = 3.3v v ext = 2.5v v ext = 1.8v gpio_ output high voltage vs. source current (push-pull) max14830 toc03 v oh (v) i source (ma) 3 2 1 10 20 30 40 50 60 70 0 0 4 v ext = 3.3v v ext = 2.5v v ext = 1.8v internal oscillator frequency vs. temperature max14830 toc02 temperature (c) internal oscillator frequency (khz) 60 35 10 -15 602 604 606 608 610 612 614 616 618 620 600 -40 85 internal oscillator frequency vs. v a voltage max14830 toc01 v a (v) internal oscillator frequency (khz) 3.35 3.10 2.85 2.60 602 604 606 608 610 612 614 616 618 620 600 2.35 3.60
max14830 quad serial uart with 128-word fifos and internal oscillator 15 pin configuration pin description top view max14830 tqfn (7mm 7mm) 13 14 15 16 17 18 19 20 21 22 23 24 gpio2 gpio3 rx0 tx0 gpio4 gpio5 gpio6 gpio7 48 47 *ep *connect ep to agnd. 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 v 18 v a agnd xin xout v ext tx3 rx3 cts3 rts3 gpio15 gpio14 gpio1 gpio0 dgnd v l rst mosi/a1 sclk/scl miso/sda ldoen 36 35 34 33 32 31 30 29 28 27 26 25 rx1 tx1 gpio8 gpio9 gpio10 gpio11 rx2 tx2 gpio12 gpio13 spi/i2c cs/a0 irq rts0 cts0 rts1 rts2 cts2 cts1 + pin name function 1 spi/i2c spi or active-low i 2 c selector input. drive spi/ i2c high to enable spi. drive spi/i2c low to enable i 2 c. 2 ldoen ldo enable input. drive ldoen high to enable the internal 1.8v ldo. drive ldoen low to disable the internal ldo. when ldoen is low, v 18 can be supplied by an external voltage source. 3 miso/sda serial-data output. when spi/ i2c is high, miso/sda functions as the miso, spi serial-data output. when spi/ i2c is low, miso/sda functions as the sda, i 2 c serial-data input/output. 4 sclk/scl serial-clock input. when spi/ i2c is high, sclk/scl functions as the sclk, spi serial-clock input (up to 26mhz). when spi/ i2c is low, sclk/scl functions as the scl, i 2 c serial-clock input (up to 1mhz). 5 cs/a0 active-low chip-select and address 0 input. when spi/ i2c is high, cs /a0 functions as the cs , spi active-low chip-select input. when spi/ i2c is low, cs /a0 functions as the a0, i 2 c device address pro - gramming input. connect cs /a0 to sda, scl, dgnd, or v l when spi/ i2c is low. 6 mosi/a1 serial-data and address 1 input. when spi/ i2c is high, mosi/a1 functions as the mosi, spi serial- data input. when spi/ i2c is low, mosi/a1 functions as the a1, i 2 c device address programming input. connect mosi/a1 to sda, scl, dgnd, or v l when spi/ i2c is low. 7 irq active-low interrupt open-drain output. irq is asserted when an interrupt is pending. 8 rst active-low reset input. drive rst low to force all of the uarts into hardware reset mode. in hardware reset mode, the oscillator and the internal pll are shut down and there is no clock activity.
max14830 quad serial uart with 128-word fifos and internal oscillator 16 pin description (continued) pin name function 9 v l digital interface logic-level supply. v l powers the internal logic-level translators for rst, irq , mosi/ a1, cs /a0, sclk/scl, miso/sda, ldoen, and spi/i2c . bypass v l with a 0.1 f f ceramic capacitor to dgnd. 10 dgnd digital ground 11 gpio0 general-purpose input/output 0. gpio0 is user-programmable as an input or output (push-pull or open drain) or external event interrupt source. gpio0 has a weak pulldown resistor to ground. gpio0 is the reference clock output when bit 7 of the txsynch register is set to 1 (see the uart clock to gpio sec - tion for more information). 12 gpio1 general-purpose input/output 1. gpio1 is user-programmable as an input or output (push-pull or open drain) or external event interrupt source. gpio1 has a weak pulldown resistor to ground. gpio1 is the timer output when bit 7 of the timer2 register is set to 1. 13 gpio2 general-purpose input/output 2. gpio2 is user-programmable as an input or output (push-pull or open drain) or external event interrupt source. gpio2 has a weak pulldown resistor to ground. 14 gpio3 general-purpose input/output 3. gpio3 is user-programmable as an input or output (push-pull or open drain) or external event interrupt source. gpio3 has a weak pulldown resistor to ground. 15 rts0 active-low request-to-send output for uart0. rts0 can be set high or low by programming the lcr register. rts0 is the uart system clock/fractional divider output when bit 7 of the clksource register is set to 1. 16 cts0 active-low clear-to-send input for uart0. cts0 is a flow control status input. 17 rx0 serial receiving data input for uart0. rx0 has a weak pullup to v ext . 18 tx0 serial transmitting data output for uart0 19 gpio4 general-purpose input/output 4. gpio4 is user-programmable as an input or output (push-pull or open drain) or external event interrupt source. gpio4 has a weak pulldown resistor to ground. gpio4 is the reference clock output when bit 7 of the txsynch register is set to 1 (see the uart clock to gpio sec - tion for more information). 20 gpio5 general-purpose input/output 5. gpio5 is user-programmable as an input or output (push-pull or open drain) or external event interrupt source. gpio5 has a weak pulldown resistor to ground. gpio5 is the timer output when bit 7 of the timer2 register is set to 1. 21 gpio6 general-purpose input/output 6. gpio6 is user-programmable as an input or output (push-pull or open drain) or external event interrupt source. gpio6 has a weak pulldown resistor to ground. 22 gpio7 general-purpose input/output 7. gpio7 is user-programmable as an input or output (push-pull or open drain) or external event interrupt source. gpio7 has a weak pulldown resistor to ground. 23 rts1 active-low request-to-send output for uart1. rts1 can be set high or low by programming the lcr register. rts1 is the uart system clock/fractional divider output when bit 7 of the clksource register is set to 1. 24 cts1 active-low clear-to-send input for uart1. cts1 is a flow control status input. 25 rx1 serial receiving data input for uart1. rx1 has a weak pullup to v ext . 26 tx1 serial transmitting data output for uart1 27 gpio8 general-purpose input/output 8. gpio8 is user-programmable as an input or output (push-pull or open drain) or external event interrupt source. gpio8 has a weak pulldown resistor to ground. gpio8 is the reference clock output when bit 7 of the txsynch register is set to 1 (see the uart clock to gpio sec - tion for more information).
max14830 quad serial uart with 128-word fifos and internal oscillator 17 pin description (continued) pin name function 28 gpio9 general-purpose input/output 9. gpio9 is user-programmable as an input or output (push-pull or open drain) or external event interrupt source. gpio9 has a weak pulldown resistor to ground. gpio9 is the timer output when bit 7 of the timer2 register is set to 1. 29 gpio10 general-purpose input/output 10. gpio10 is user-programmable as an input or output (push-pull or open drain) or external event interrupt source. gpio10 has a weak pulldown resistor to ground. 30 gpio11 general-purpose input/output 11. gpio11 is user-programmable as an input or output (push-pull or open drain) or external event interrupt source. gpio11 has a weak pulldown resistor to ground. 31 rts2 active-low request-to-send output for uart2. rts2 can be set high or low by programming the lcr register. rts2 is the uart system clock/fractional divider output when bit 7 of the clksource register is set to 1. 32 cts2 active-low clear-to-send input for uart2. cts2 is a flow control status input. 33 rx2 serial receiving data input for uart2. rx2 has a weak pullup to v ext . 34 tx2 serial transmitting data output for uart2 35 gpio12 general-purpose input/output 12. gpio12 is user-programmable as an input or output (push-pull or open drain) or external event interrupt source. gpio12 has a weak pulldown resistor to ground. gpio12 is the reference clock output when bit 7 of the txsynch register is set to 1 (see the uart clock to gpio section for more information). 36 gpio13 general-purpose input/output 13. gpio13 is user-programmable as an input or output (push-pull or open drain) or external event interrupt source. gpio13 has a weak pulldown resistor to ground. gpio13 is the timer output if bit 7 of the timer2 register is set to 1. 37 gpio14 general-purpose input/output 14. gpio14 is user-programmable as an input or output (push-pull or open drain) or external event interrupt source. gpio14 has a weak pulldown resistor to ground. 38 gpio15 general-purpose input/output 15. gpio15 is user-programmable as an input or output (push-pull or open drain) or external event interrupt source. gpio15 has a weak pulldown resistor to ground. 39 rts3 active-low request-to-send output for uart3. rts3 can be set high or low by programming the lcr register. rts3 is the uart system clock/fractional divider output when bit 7 of the clksource register is set to 1. 40 cts3 active-low clear-to-send input for uart3. cts3 is a flow control status input. 41 rx3 serial receiving data input for uart3. rx3 has a weak pullup to v ext . 42 tx3 serial transmitting data output for uart3 43 v ext transceiver interface level supply. v ext powers the internal logic-level translators for rx_, tx_, rts_, cts_ , and gpio_. bypass v ext with a 0.1 f f ceramic capacitor to dgnd. 44 xout crystal output. when using an external crystal, connect one end of the crystal to xout and the other to xin. when using an external clock source or the internal oscillator, leave xout unconnected. 45 xin crystal/clock input. when using an external crystal, connect one end of the crystal to xin and the other one to xout. when using an external clock source, drive xin with the external clock. when using the internal oscillator, leave xin unconnected. 46 agnd analog ground 47 v a analog supply. v a powers the internal oscillators, the pll, and the internal ldo. bypass v a with a 0.1f f ceramic capacitor to agnd. 48 v 18 internal 1.8v ldo output and 1.8v logic supply input. bypass v 18 with a 0.1 f f ceramic capacitor to dgnd. ep exposed paddle. connect ep to agnd. do not use ep as the main agnd connection.
max14830 quad serial uart with 128-word fifos and internal oscillator 18 detailed description the max14830 quad uart bridges an spi/microwire? or i 2 c microprocessor bus to an asynchronous interface like rs-485, rs-232, or irda. the max14830 contains advanced uarts and baud-rate generators with a synchronous serial-data interface and an interrupt gen - erator. the max14830 is configured by writing an 8-bit word to the configuration registers through either spi or i 2 c. these registers are organized by related function as shown in the register map . the host controller loads transmit data into the thr register through spi or i 2 c. this data is automatically pushed into the transmit fifos, formatted, and sent out at tx_. the max14830 adds start and stop and par - ity bits to the data and sends the data out at the selected baud rates. the clock configuration registers determine the baud rates, clock source selection, clock frequency prescaling, and fractional baud-rate generators. the max14830 receiver detects a start bit as a high- to-low rx_ transition. an internal clock samples this data at 16 times the data rate. the received data is automati - cally placed in the receive fifos and can then be read out of the rxfifos through the rhrs. the max14830 features four identical uarts. text in this data sheet references individual uart operation, unless otherwise noted. receive and transmit fifos the uarts receiver and the transmitter each have a 128-word deep fifo reducing the intervals that the host processor needs to dedicate for high-speed, high- volume data transfer. as the data rates of the asynchro - nous rx_ and tx_ interfaces increase and get closer to those of the host controllers spi/i 2 c data rates, uart management and flow control can make up a significant portion of the hosts activity. by increasing fifo size, the host is interrupted less often and can utilize spi and i 2 c burst data block transfers to/from the fifos. fifo trigger levels can generate interrupts to the host controller, signaling that programmed fifo fill levels have been reached. the transmitter and receiver trig - ger levels are programmed through fifotriglvl with a resolution of eight fifo locations. when a receive fifo trigger is generated, the host knows that the receive fifo has a defined number of words waiting to be read out or that a known number of vacant fifo locations are available, ready to be filled. the transmit fifo trigger generates an interrupt when the transmit fifo level is above the programmed trigger level. the host then knows to throttle data writing to the transmit fifo. the host can read out the number of words present in each of the fifos at any time through the txfifolvl and rxfifolvl registers. transmitter operation figure 3 shows the structure of the transmitter with the txfifo. the transmit fifo can hold up to 128 words that are written to it through the transmit holding register (thr). the current number of words in the txfifo can be read out through the txfifolvl register. the transmit fifo can be programmed to generate an interrupt when a programmed number of words are present in the txfifo through the fifotrglvl register. the txfifo interrupt trigger level is selectable through fifotrglvl[3:0]. when the transmit fifo fill level reaches the programmed trig - ger level, the isr[4] interrupt is set. the transmit fifo is empty when isr[5]:tfifoemptyint is set. isr[5] turns high when the transmitter starts trans - mitting the last word in the txfifo. hence the transmitter is completely empty after isr[5] is set with an addi - tional delay equal to the length of a complete character (including start, parity, and stop bits). microwire is a trademark of national semiconductor corp. figure 3. transmit fifo signals data from spi/i 2 c interface thr 128 trigger isr[4] txfifolvl fifo trglvl[3:0] current fill level transmit fifo transmit shift-register tx_ 3 2 1 level empty isr[5]
max14830 quad serial uart with 128-word fifos and internal oscillator 19 the contents of the txfifo and rxfifos are both cleared through mode2[1]: fiforst. to halt transmission, set mode1[1]: txdisabl to 1. after mode1[1] is set, the transmitter completes transmission of the current character and then ceases transmission. the tx_ output logic can be inverted through irda[5]: txinv. if not stated otherwise, all transmitter logic described in this data sheet assumes that irda[5] is 0. receiver operation the receiver expects the format of the data at rx_ to be as shown in figure 4. the quiescent logic state is high and the first bit (the start bit) is logic-low. the receiver samples the data near the midbit instant (figure 4). the received words and their associated errors are depos - ited into the receive fifo. errors and status informa - tion are stored for every received word (figure 5). the host reads the data out of the receive fifo through the receive holding register (rhr), oldest data first. the status information of the current word in the rhr is located in the line status register (lsr). after a word is read out of the rhr, the lsr contains the status informa - tion for that word. the following three error conditions are determined for each received word: parity error, framing error, and noise on the line. line noise is detected by checking the consistency of the logic of the three samples (figure 6). figure 5. receive fifo figure 4. receive data format figure 6. midbit sampling received data lsb start d0 d1 d2 d3 d4 d5 d6 d7 parity stop stop msb middata sampling receive fifo fifotrglvl[7:4] trigger isr[3] word error 128 rxfifolvl 4 3 2 1 timeout empty errors overrun lsr[1] received data rhr receiver rx_ i 2 c/spi interface lsr[0] isr[6] lsr[5:2] current fill level 1 rx_ baud block 2 3 4 5 6 7 8 9 one bit period 10 11 majority center sampler 12 13 14 15 16 a
max14830 quad serial uart with 128-word fifos and internal oscillator 20 the receiver can be turned off through mode1[0]: rxdisabl. when this bit is set to 1, the max14830 turns the receiver off immediately following the current word and does not receive any further data. the rx_ input logic can be inverted through irda[4]: rxinv. line noise indication when operating in standard or 2x (i.e. not 4x) rate mode, the max14830 checks that the binary logic level of the three samples per received bit are identical. if any of the three samples have differing logic levels, then noise on the transmission line has affected the received data and is considered to be noisy. this noise indication is reflected in the lsr[5]: rxnoise bit for each received byte. parity errors are another indication of noise, but are not as sensitive. clocking and baud-rate generation the max14830 can be clocked by its internal oscillator, an external crystal, or an external clock source. figure 7 shows a simplified diagram of the clocking circuitry. when the max14830 is clocked by the internal oscillator or a crystal, the stsint[5]: clockready indicates when the clocks have settled and the baud-rate generator is ready for stable operation. each uart baud rate can be individually programmed. the baud-rate clock can be routed to the rts_ output. the clock rate of this is 16x the baud rate in standard operating mode and 8x the baud rate in 2x rate mode. in 4x rate mode, the clkout frequency is 4x the programmed baud rate. if the fractional portion of the baud-rate generator is used, the clock is not regular and exhibits jitter. internal oscillator the internal 614.4khz oscillator does not require exter - nal components and provides a source for baud-rate generation. to achieve common baud rates, the inter - nal oscillator requires the use of the internal pll (see the pll section). set clksource[4]: extclock to 0 and clksource[0]: intoscen to 1 to select and enable the internal oscillator. crystal oscillator if a higher baud-rate accuracy or low power consump - tion is required, the crystal oscillator or an external clock source can be used. set clksource[4]: extclock to 1 and clksource[1]: crystalen to 1 to enable and select the crystal oscillator. the on-chip crystal oscillator has load capacitances of 16pf (typ) integrated in both xin and xout. connect an external crystal or ceramic oscil - lator between xin and xout. external clock source connect an external clock source to xin when not using the internal oscillator or a crystal oscillator. leave xout unconnected. set clksource[4]: extclock to 1 and clksource[1]: crystalen to 0 to select external clocking. pll and predivider the internal predivider and pll allow for a wide range of external clock frequencies and baud rates. the pll can be configured to multiply the input clock rate by a factor of 6, 48, 96, or 144 through the pllconfig register. the predivider, located between the input clock and the pll, allows division of the input clock by a factor between 1 and 63 by writing to pllconfig[5:0]. see the pllconfig register description for more information. figure 7. clock selection diagram pllbyps extclock crystalen xout crystal oscillator internal oscillator intoscen pllen xin divider pll fractional baud-rate generator 1 fractional baud-rate generator 2 fractional baud-rate generator 3 fractional baud-rate generator 0
max14830 quad serial uart with 128-word fifos and internal oscillator 21 fractional baud-rate generators the internal fractional baud-rate generator provides a high degree of flexibility and high resolution in baud- rate programming. the baud-rate generator has a 16-bit integer divisor and a 4-bit word for the fractional divisor. the fractional baud-rate generator can be used either with the internal oscillator or with the external crystal or clock source. the integer and fractional divisors are calculated through the divisor, d: ref f d 16 baudrate = where f ref is the reference frequency input to the baud- rate generator and d is the ideal divisor. in 2x and 4x rate modes, replace the divisor 16 by 8 or 4, respectively. the integer divisor portion, div, of the divisor, d, is obtained by truncating d: div = trunc(d) div can be a maximum of 16 bits wide and is pro - grammed into the 2-byte-wide registers divmsb and divlsb. the minimum allowed value for divlsb is 1. the fractional portion of the divisor, fract, is a 4-bit nibble, which is programmed into brgconfig[3:0]. the maximum value is 15, allowing the divisor to be pro - grammed with a resolution of 0.0625. fract is calcu - lated as: fract = round(16 x (d-div)). the following is an example of calculating the divisor. it is based on a required baud rate of 190kbaud and a reference input frequency of 28.23mhz and default rate mode. the ideal divisor is calculated as: d = 28,230,000 / (16 x 190,000) = 9.286 hence div = 9. fract = round(4.579) = 0x05 so that divmsb = 0x00, divlsb = 0x09, and brgconfig[3:0] = 0x05. the resulting actual baud rate can be calculated as: ref actual actual f br 16 d = for this example: d actual = 9 + 5/16 = 9.313, where d actual = div + (fract/16) and br actual = 28,230,000 / (16 x 9.3125) = 189,463.087 baud. thus the baud rate is within 0.000028% of the ideal rate. 2x and 4x rate modes to support higher baud rates than possible with stan - dard (16x sampling) operation, the max14830 offers 2x and 4x rate modes. in this case, the reference clock rate only needs to be either 8x or 4x of the baud rate, respec - tively. in 4x mode only, the bits are only sampled once, at the midbit instant, instead of the usual three samples to determine the logic value of the bits. this reduces the tolerance to line noise on the received data. the 2x and 4x modes are selectable through brgconfig[5:4]. note that irda encoding and decoding does not operate in 2x and 4x modes. when 2x rate mode is selected, the actual baud rate is twice the rate programmed into the baud-rate genera - tor. if 4x rate mode is enabled, the actual baud rate on the line is quadruple that of the programmed baud rate (figure 8). figure 8. 2x and 4x baud rates fractional rate generator divlsb divmsb fract note: irda does not work in 2x and 4x modes. f ref brgconfig[5:4] rate mode selection 1 x baud rate, 2 x baud rate, 4 x baud rate
max14830 quad serial uart with 128-word fifos and internal oscillator 22 low-frequency timer the general-purpose timer can be used to generate a low-frequency clock at a gpio output and can, for exam - ple, be used to drive external leds. the low-frequency clock is a divided replica of a given uart baud-rate clock. the timer is internally routed to the gpio_ outputs when enabled in the timer2 register as follows: ? uart0: gpio1 ? uart1: gpio5 ? uart2: gpio9 ? uart3: gpio13 the clock pulses at the gpios are generated at a rate defined by the baud-rate generator and the timer divider (figure 9). the baud-rate generator clock is divided by (1024 x timerx), where timerx is a 15-bit integer pro - grammed into the timer1 and timer2 registers. the timer output is a 50% duty cycle clock. uart clock to gpio the max14830 reference clock can be routed to the gpio0, gpio4, gpio8, and/or gpio12 outputs in case a synchronous high-frequency clock is needed by another device. enable routing a uart clock to gpio0, gpio4, gpio8, and/or gpio12 in the txsynch register. this out - put clock could, for example, be used to clock another uart device (figure 29). multidrop mode in multidrop mode, also known as 9-bit mode, the word length is 8 bits and a 9th bit is used for distinguishing between an address and a data word. multidrop mode is enabled through mode2[6]: multidrop. parity checking is disabled and an spclcharint[5]: multidropint interrupt is generated when an address (9th bit set) is received. it is up to the host processor to filter out the data intended for its address. alternatively the auto data filtering mode can be used to automatically filter out the data intended for the stations specific 9-bit mode address. auto data filtering in multidrop mode in multidrop mode, the max14830 can be configured to automatically filter out data that is not meant for its address. the address is user-definable either by pro - gramming a register value or a combination of a register value and gpio hardware inputs. use either xoff2 or xoff2[7:4] in combination with gpio_ to define the address. enable multidrop mode by setting mode2[6]: multidrop to 1 and enable auto data filtering by setting mode2[4]: specialchr to 1. when using register bits in combination with gpio_ to define the address, the msb of the address is written to xoff2[7:4] register bits, while the lsbs of the address are defined through the gpios. to enable this mode, set flowctrl[2]: gpiaddr, mode2[4]: specialchr, and mode2[6]: multidrop to 1. gpio_ are automatically read when flowctrl[2]: gpiaddr is set to 1, and the address is updated on logic changes at gpio_. in the auto data filtering mode, the max14830 auto - matically accepts data that is meant for its address and places this into the receive fifo, while it discards data that is not meant for its address. the received address word is not put into the fifo. auto transceiver direction control in some half-duplex communication systems the trans - ceivers transmitter must be turned off when data is being received so as not to load the bus. this is the case in half-duplex rs-485 communication. similarly in full-duplex multidrop communication, like rs-485 or rs-422/v.11, only one transmitter can be enabled at any one time and the others must be disabled. the max14830 can automatically enable/disable a trans - ceivers transmitter and/or receiver. this relieves the host processor of this time-critical task. the rts_ output is used to control the transceivers transmit enable input and is automatically set high when the max14830s transmitter starts transmission. figure 9. gpio_ clock pulse generator uart_ fractional rate generator f ref timerx gpio_ gpio_ tmrtogpio divide-by-1024
max14830 quad serial uart with 128-word fifos and internal oscillator 23 this occurs as soon as data is present in the transmit fifo. auto transceiver direction control is enabled through mode1[4]: trnscvctrl. figure 10 shows a typical max14830 connection in a rs-485 application. the rts_ output can be set high in advance of tx_ transmission by a programmable time period called the setup time (figure 11). the setup time is programmed through hdplxdelay[7:4]. similarly, the rts_ signal can be held high for a programmable period after the transmitter has completed transmission. the hold time is programmed through hdplxdelay[3:0]. transmitter triggering and synchronization the max14830 allows synchronization of transmitters so that selected uarts start transmitting data when a trigger command is received. optional delays can also be programmed, which delay the start of transmission after a trigger command is received. a uarts transmit - ter can be assigned one of 16 possible spi/i 2 c trigger commands. a trigger command is defined as any of 16 special values written into the globlcomnd register (see the globlcomnd section for more information). when a byte is written into the globlcomnd register, uart select bits (u0 and u1) are ignored by the max14830, and the globlcomnd applies to all four uarts. transmission is initiated when the max14830 receives the assigned spi/ i 2 c trigger command if the selected transmitter is initially disabled and data has been loaded into its txfifo. enable and configure transmitter synchronization in the txsynch register. triggering and synchronization requires that the txfifos are disabled before the trigger is received. this can be done by setting the mode1[1] bit to 1 or by utilizing the auto transmitter disable function (txsynch[4] is 1). transmitter synchronization synchronize multiple uarts so their transmitters start transmission simultaneously by assigning a common trigger command to the uarts that should be synchro - nized. intrachip and interchip synchronization intrachip transmitter triggering occurs when any of the four uarts in a max14830 are triggered by one trigger command. this type of synchronization is supported in both spi and i 2 c modes, as the trigger commands are global commands that are received by all four uarts simultaneously. interchip transmitter triggering occurs when the uarts in different max14830 devices are synchronized. this type of synchronization is achievable in spi mode only. pull the cs of all the max14830 devices on the bus low during the spi masters write trigger command so that the commands are received by all uarts on the shared spi bus. i 2 c protocol does not allow simultaneous addressing of multiple devices. delayed triggering a delay can be programmed for delaying the start of transmission after the reception of an assigned trig - ger command. set the delay by programming the synchdelay1 and synchdelay2 registers. figure 11. setup and hold times in auto transceiver direction control figure 10. auto transceiver direction control tx_ di d b a r de re ro rts_ rx_ tx fifo rx fifo max14830 transmitter auto transceiver control receiver max14840e tx_ first character last character rts_ setup hold
max14830 quad serial uart with 128-word fifos and internal oscillator 24 trigger accuracy the delay between the time when the max14830 receives a trigger command and the time when the associated transmitter starts transmission is made up of a fixed, deterministic portion and a variable, random component. both portions of the delay are dependent on the uarts clock and baud rates. when the fractional divider is not used, the intrinsic trigger delay, t trig , is bounded by the following limits: trig 5 br 6 br t 16 16 where br is the fractional divider output clock period. this equation is independent on the rate mode. the reference point is the time when the trigger command is received by the max14830. this occurs on the final (i.e. the 16th) spi clocks low-to-high transition (figure 12). when the fractional baud-rate generator is used, the random portion is larger than one uart clock period. synchronization accuracy when synchronizing multiple uart transmitters, the accuracy of the tx_ transmitter outputs is based on the triggering delays of each uart (figure 13). this skew has a baud-rate dependent component, similar to the trigger accuracy equation for a single transmitter output. calculate the tx_ transmitter output skew using the fol - lowing equation: ( ) s f trigskew 6 br 5 br t max 16 ? where br s is the fractional divider output clock of the lower/slower baud-rate uart and br f is the fractional divider output clock of the higher/faster baud-rate uart. auto transmitter disable the max14830 allows automatic disabling of the trans - mitter. enable auto transmitter disabling functionality by setting txsynch[4] to 1. when auto transmitter disabling is activated, the max14830 disables the specified transmitter after it completes sending all the data in its txfifo. new data can then be loaded into the txfifo. a disabled transmitter does not send out data on the tx_ output when data is present in its txfifo. to enable transmission, either clear the txautodis bit in the txsynch register or toggle the txdisabl bit in the mode1 register. echo suppression the max14830 can suppress echoed data, sometimes found in half-duplex communication (e.g. rs-485 and irda). if the transceivers receiver is not turned off while the transceiver is transmitting, copies (echoes) are received by the uart. the max14830s receiver can block the reception of this echoed data by enabling echo suppression. set mode2[7]: echosuprs to 1 to enable echo suppression. the max14830 receiver can block echoes with a long round trip delay. the transmitter can be configured to remain enabled after the end of transmission for a pro - grammable period of time: the hold time delay (figure 14). the hold time delay is set by the hdplxdelay[3:0] register. see the hdplxdelay register section for more information. figure 12. single transmitter trigger accuracy uncertainty interval t trig_min t trig_max tx_ sclk
max14830 quad serial uart with 128-word fifos and internal oscillator 25 figure 13. multiple transmitter synchronization accuracy figure 14. echo suppression timing t tx1_max t trigskew t tx1_min t tx0_max t tx0_min tx0 tx1 sclk tx_ rx_ di to ro propagation delay hold delay stop bit rts_
max14830 quad serial uart with 128-word fifos and internal oscillator 26 echo suppression can operate simultaneously with auto transceiver direction control (figure 15). auto hardware flow control the max14830 is capable of automatic hardware (rts and cts) flow control without the need for host proces - sor intervention. when autorts control is enabled, the max14830 automatically controls the rts hand - shake without the need for host processor intervention. autocts flow control separately turns the max14830s transmitter on and off based on the cts_ input. autorts and autocts flow control are independently enabled through flowctrl[1:0]. autorts control autorts flow control ensures that the receive fifo does not overflow by signaling to the far end uart to stop data transmission. the max14830 does this automatical - ly by controlling rts_ . autorts flow control is enabled through flowctrl[0]: autorts. the halt and resume levels determine the threshold levels at which rts_ is asserted and deasserted. halt and resume are pro - grammed in flowlvl. with differing halt and resume levels, hysteresis can be defined for the rts_ transitions. when the rxfifo fill level reaches the halt level (flowlvl[3:0]), the max14830 deasserts rts_. rts_ remains deasserted until the rxfifo is emptied and the number of words falls to the resume level. interrupts are not generated when the halt and resume levels are reached. this allows the host control - ler to be completely disengaged from rts flow control management. autocts control when autocts flow control is enabled, the uart auto - matically starts transmitting data when the cts_ input is logic-level low and stops transmitting when cts_ is logic-high. this frees the host processor from manag - ing this timing-critical flow control task. autocts flow control is enabled through flowctrl[1]: autocts. during autocts flow control, the cts interrupt works normally. set the irqen[7]: ctsinten to 0 to disable cts interrupts then isr[7]: ctsint is fixed to logic 0 and the host does not receive interrupts from cts_ . if cts_ is set high dur- ing transmission the max14830 completes transmission of the current word and halts transmission afterwards. turn the transmitter off by setting mode1[1] to 1 before enabling autocts control. fifo interrupt triggering receive and transmit fifo fill-dependent interrupts are generated if fifo trigger levels are defined. when the number of words in the fifos reach or exceed a trigger level, as programmed in fifotrglvl, an isr[3] or isr[4] interrupt is generated. there is no relationship between the trigger levels and the halt or resume levels. the fifo trigger level can, for example, be used for a block data transfer, since it gives the host an indication when a given block size of data is available for reading in the receive fifo or available for transfer to the transmit fifo. auto software (xon/xoff) flow control when auto software flow control is enabled, the max14830 recognizes and/or sends predefined xon/ xoff characters to control the flow of data across the asynchronous serial link. automatic flow works autono - mously and does not involve host intervention, similar to auto hardware flow control. to reduce the chance of receiving corrupted data that equals a single-byte xon or xoff character, the max14830 allows for double wide (16-bit) xon/xoff characters. xon and xoff are programmed into the xon1, xon2 and xoff1, xoff2 registers. flowctrl[7:3] are used for enabling and configuring auto software flow control. an isr[1] interrupt is generated when xon or xoff are received and details are found in spclcharint. the irq can be masked by setting irqen[1]: spclchrien to 0. software flow control consists of transmitter control and receiver overflow control, which can operate indepen - dently of one another. figure 15. half-duplex with echo suppression tx lo gi c transmitter tx_ di d b a r de re ro rts_ rx_ echo suppression receiver rx fifo tx fifo max14840e max14830
max14830 quad serial uart with 128-word fifos and internal oscillator 27 transmitter control when auto transmitter control (flowctrl[5:4]) is enabled, the receiver compares all received words with the xoff and xon characters. if an xoff character is received, the max14830 halts its transmitter from sending further data. the receiver is not affected and continues reception. upon receiving xon, the transmitter then restarts sending data. the received xon and xoff characters are filtered out and are not put into the receive fifo, as they do not have significance to the higher layer protocol. turn the transmitter off (mode1[1] = 1) before enabling transmitter control. receiver overflow control when auto receiver overflow control (flowctrl[7:6]) is enabled, the max14830 automatically sends xoff and xon control characters to the far end uart to avoid receiver overflow. xoff1/xoff2 is/are sent when the receive fifo fill level reaches the halt value set in the flowlvl register. when the host controller reads data from the receive fifo to a level equal to the resume level programmed into the flowlvl register, xon1/xon2 is/are automatically sent to the far end station to signal it to resume data transmission. xon1/xoff1 is transmitted before xon2/xoff2 when dual character (xon1 and xon2/xoff1 and xoff2) flow control is enabled. power-up and irq irq has two functions. during normal operation (mode1[7] = 1), irq operates as a hardware interrupt output, whereby the irq is active when an interrupt is pending. an irq interrupt can only be produced during normal operation if at least one of the irqen interrupt enable bits are enabled. during power-up or following a reset, irq has a different function. it is held low until the max14830 is ready for programming following an initialization delay. once irq goes high, the max14830 is ready to be programmed. the mode1[7]: irqsel bit should then be set to enable normal irq interrupt operation. in polled mode, the divlsb register can be polled to check whether the max14830 is ready for operation. if the controller gets a valid response from divlsb, then the max14830 is ready for operation. shutdown mode pull rst to dgnd to enter shutdown mode. shutdown mode is the lowest power consumption mode. in shut - down mode, all of the max14830 circuitry is off. this includes the spi/i 2 c interface, the registers, the fifos, and clocking circuitry. the ldo is on in shutdown mode. when the rst input is high, the max14830 exits shut- down mode. the chip initialization is completed when the max14830 sets irq to logic-high. the max14830 needs to be reprogrammed following a shutdown. interrupt structure the structure of the interrupt is shown in figure 16. there are four interrupt source registers for each uart: isr, lsr, stsint, and spclcharint. read the globalirq register to determine which uart is the source of the figure 16. simplified interrupt structure 7 6 5 4 3 lsr 2 1 0 7 6 5 4 3 stsint 2 1 0 0 0 0 0 globalirq 7 6 5 4 3 isr 2 1 0 7 6 5 4 3 isr low-level interrupt s top-level interrupts 2 1 0 7 6 5 4 3 isr 2 1 0 7 6 5 4 3 isr 2 1 0 7 6 5 4 3 spclcharint 2 1 0 irq3 irq irq1 irq0 irq2 8 8 8 8 8 8 8 4 [3] [0]
max14830 quad serial uart with 128-word fifos and internal oscillator 28 interrupt. the interrupt sources are divided into top-level and low-level interrupts. the top-level interrupts typically occur more often and can be read out directly through the isr. the low-level interrupts typically occur less often and their specific source can be read out through the lsr, stsint, or spclchar registers. the three lsbs of the isr point to the low-level interrupt registers that contain the detail of the interrupt source. interrupt enabling every interrupt bit of the four interrupt registers can be enabled or masked through an associated interrupt enable register bit. these are the irqen, lsrinten, spclchrinten, and stsinten registers. interrupt clearing when an isr interrupt is pending (i.e. any bit in isr is set) and the isr is subsequently read, the isr bits and irq are cleared. both the spclcharint and the stsint registers are also clear on read (cor). the lsr bits are only cleared when the source of the interrupt is removed, not when lsr is read. reading the globalirq register does not clear the irq interrupt. register map (all default reset values are 0x00, unless otherwise noted. all registers are r/w, unless otherwise noted.) register addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 fifo data rhr ? 0x00 rdata7 rdata6 rdata5 rdata4 rdata3 rdata2 rdata1 rdata0 thr ? 0x00 tdata7 tdata6 tdata5 tdata4 tdata3 tdata2 tdata1 tdata0 interrupts irqen 0x01 ctsien rfifoemtyien tfifoemtyien tfifotrgien rfifotrgien stsien spclchrien lsrerrien isr* ? 0x02 ctsint rfifoemptyint tfifoemptyint tfifotrigint rfifotrigint stsint spcharint lsrerrint lsrinten 0x03 rxnoiseinten rbreakien frameerrien parityien roverrien rtimoutien lsr* ? 0x04 ctsbit rxnoise rxbreak frameerr rxparityerr rxoverrun rtimeout spclchrinten 0x05 mltdrpinten breakinten xoff2inten xoff1inten xon2inten xon1inten spclcharint ? 0x06 multidropint breakint xoff2int xoff1int xon2int xon1int stsinten 0x07 clockrdyinten gpi3inten gpi2inten gpi1inten gpi0inten stsint ? 0x08 clockready gpi3int gpi2int gpi1int gpi0int uart modes mode1 0x09 irqsel trnscvctrl rtshiz txhiz txdisabl rxdisabl mode2 0x0a echosuprs multidrop loopback specialchr rxemtyinv rxtrginv fiforst rst lcr* 0x0b rtsbit txbreak forceparity evenparity parityen stopbits length1 length0 rxtimeout 0x0c timout7 timout6 timout5 timout4 timout3 timout2 timout1 timout0 hdplxdelay 0x0d setup3 setup2 setup1 setup0 hold3 hold2 hold1 hold0 irda 0x0e txinv rxinv mir shortir sir irdaen fifos control flowlvl 0x0f resume3 resume2 resume1 resume0 halt3 halt2 halt1 halt0 fifotrglvl* 0x10 rxtrig3 rxtrig2 rxtrig1 rxtrig0 txtrig3 txtrig2 txtrig1 txtrig0 txfifolvl ? 0x11 txfl7 txfl6 txfl5 txfl4 txfl3 txfl2 txfl1 txfl0 rxfifolvl ? 0x12 rxfl7 rxfl6 rxfl5 rxfl4 rxfl3 rxfl2 rxfl1 rxfl0 flow control flowctrl 0x13 swflow3 swflow2 swflow1 swflow0 swflowen gpiaddr autocts autorts xon1 0x14 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 xon2 0x15 bit7 bi6 bit5 bit4 bit3 bit2 bit1 bit0 xoff1 0x16 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 xoff2 0x17 bit7 bi6 bit5 bit4 bit3 bit2 bit1 bit0
max14830 quad serial uart with 128-word fifos and internal oscillator 29 register map (continued) * denotes nonzero default reset value: isr = 0x60, lcr = 0x05, fifotrglvl = 0xff, pllconfig = 0x01, divlsb = 0x01, clksource = 0x08, revid = 0xb1. ?denotes nonread/write value: rhr = r, thr = w, isr = cor, spclcharint = cor, stsint = r/cor, lsr = r, txfifolvl = r, rxfifolvl = r, revid = r. each uart has four individually assigned gpio outputs as follows: uart0: gpio0Cgpio3, uart1: gpio4Cgpio7, uart2: gpio8Cgpio11, uart3: gpio12Cgpio15. ?this register can only be programmed by accessing uart0. #this register can only be directly addressed in i 2 c mode. use extended addressing when operating in spi mode. register addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 gpios gpioconfg 0x18 gp3od gp2od gp1od gp0od gp3out gp2out gp1out gp0out gpiodata 0x19 gpi3dat gpi2dat gpi1dat gpi0dat gpo3dat gpo2dat gpo1dat gpo0dat clock configuration pllconfig* ? 0x1a pllfactor1 pllfactor0 prediv5 prediv4 prediv3 prediv2 prediv1 prediv0 brgconfig 0x1b 4xmode 2xmode fract3 fract2 fract1 fract0 divlsb 0x1c div7 div6 div5 div4 div3 div2 div1 div0 divmsb 0x1d div15 div14 div13 div12 div11 div10 div9 div8 clksource* ? 0x1e clktorts extclock pllbypass pllen cystalen intoscen global registers globalrq 0x1f 0 0 0 0 irq3 irq2 irq1 irq0 globlcomnd 0x1f glbcom7 glbcom6 glbcom5 glbcom4 glbcom3 glbcom2 glbcom1 glbcom0 synchronization registers txsynch # 0x20 clktogpio txautodis trigdelay synchen trigsel3 trigsel2 trigsel1 trigsel0 synchdelay1 # 0x21 sdelay7 sdelay6 sdelay5 sdelay4 sdelay3 sdelay2 sdelay1 sdelay0 synchdelay2 # 0x22 sdelay15 sdelay14 sdelay13 sdelay12 sdelay11 sdelay10 sdelay9 sdelay8 timer registers timer1 # 0x23 timer7 timer6 timer5 timer4 timer3 timer2 timer1 timer0 timer2 # 0x24 tmrtogpio timer14 timer13 timer12 timer11 timer10 timer9 timer8 revision revid* ? 0x25 1 0 1 1 0 0 0 1
max14830 quad serial uart with 128-word fifos and internal oscillator 30 detailed register description the max14830 has registers that are 8 bits wide. rhrreceiver hold register bits 7 C0: rdata[n] the rhr is the bottom of the receive fifo and is the register used for reading data out of the receive fifo. it contains the oldest (first received) character in the receive fifo. rhr[0] is the lsb of the character received at the rx_ input. it is the first data bit of the serial-data word received by the receiver. thrtransmit hold register bits 7C0: tdata[n] the thr is the register that the host controller writes data to for subsequent uart transmission. this data is deposited in the transmit fifo. thr[0] is the lsb. it is the first data bit of the serial-data word that the transmitter sends out, right after the start bit. address: 0x00 mode: r bit 7 6 5 4 3 2 1 0 name rdata7 rdata6 rdata5 rdata4 rdata3 rdata2 rdata1 rdata0 reset 0 0 0 0 0 0 0 0 address: 0x00 mode: w bit 7 6 5 4 3 2 1 0 name tdata7 tdata6 tdata5 tdata4 tdata3 tdata 2 tdata1 tdata0 reset 0 0 0 0 0 0 0 0
max14830 quad serial uart with 128-word fifos and internal oscillator 31 irqenirq enable register the irqen register is used to enable the irq physical interrupt. any of the eight isr interrupt sources can be enabled to generate an irq . the irqen bits only influence the irq output and do not have any effect on the isr contents or behavior. every one of the irqen bits operates on an isr bit. bit 7: ctsien the ctsien bit enables irq interrupt generation when the ctsint interrupt bit is set in the isr. set the ctsien bit low to disable irq generation from ctsint. bit 6: rfifoemtyien the rfifoemtyien bit enables irq interrupt generation when the rfifoemptyint interrupt bit is set in the isr. set the rfifoemtyien bit low to disable irq generation from rfifoemptyint. bit 5: tfifoemtyien the tfifoemtyien bit enables irq interrupt generation when the tfifoemptyint interrupt bit is set in the isr. set the tfifoemtyien bit low to disable irq generation from tfifoemptyint. bit 4: tfifotrgien the tfifotrgien bit enables irq interrupt generation when the tfifotrigint interrupt bit is set in the isr. set tfifotrgien bit low to disable irq generation from tfifotrigint. bit 3: rfifotrgien the rfifotrgien bit enables irq interrupt generation when the rfifotrigint interrupt bit is set in the isr. set the rfifotrgien bit low to disable irq generation from rfifotrigint. bit 2: stsien the stsien bit enables irq interrupt generation when the stsint interrupt bit is set in the isr. set the stsien bit low to disable irq generation from stsint. bit 1: spclchrien the spclchrien bit enables irq interrupt generation when the spcharint interrupt bit is set in the isr. set the spclchrien bit low to disable irq generation from spcharint. bit 0: lsrerrien the lsrerrien bit enables irq interrupt generation when the lsrerrint interrupt bit is set in the isr[0]. set the lsrerrien low to disable irq generation from lsrerrint. address: 0x01 mode: r/w bit 7 6 5 4 3 2 1 0 name ctsien rfifoemtyien tfifoemtyien tfifotrgien rfifotrgien stsien spclchrien lsrerrien reset 0 0 0 0 0 0 0 0
max14830 quad serial uart with 128-word fifos and internal oscillator 32 isrinterrupt status register the interrupt status register provides an overview of all interrupts generated in the max14830. these interrupts are cleared upon reading the isr. when the max14830 is operated in polled mode, the isr can be polled to establish the uarts status. in interrupt-driven mode, irq interrupts are enabled through the appropriate irqen bits. the isr contents give direct information on the cause for the interrupt or point to other registers that contain more detailed information. bit 7: ctsint the ctsint is set when a logic state transition occurs at the cts_ input. this bit is cleared after isr is read. the current logic state of the cts_ input can be read out through lsr[7]: cts bit. bit 6: rfifoemptyint the rfifoemptyint is set when the receive fifo is empty. this bit is cleared after isr is read. its meaning can be inverted by setting the mode2[3]: rxemtyint bit. bit 5: tfifoemptyint the tfifoemptyint bit is set when the transmit fifo is empty. this bit is cleared once isr is read. bit 4: tfifotrigint the tfifotrigint bit is set when the number of characters in the transmit fifo is equal to or greater than the transmit fifo trigger level defined in fifotriglvl[3:0]. tfifotrigint is cleared when the transmit fifo level falls below the trigger level or after the isr is read. it can be used as a warning that the transmit fifo is nearing overflow. bit 3: rfifotrigint the rfifotrigint bit is set when the receive fifo fill level reaches the receive fifo trigger level, as defined in fifotriglvl[7:4]. this can be used as an indication that the receive fifo is nearing overrun. it can also be used to report that a known number of words are available that can be read out in one block. the meaning of rfifotrigint can be inverted through mode2[2]. rfifotrigint is cleared when isr is read. bit 2: stsint the stsint bit is set high when any bit in the stsint register that is enabled through a stsinten bit is high. the stsint bit is cleared upon reading isr. bit 1: spcharint the spcharint bit is set high when a special character is received, a line break is detected or an address character is received in multidrop mode. the cause for the spcharint interrupt can be read from the spclcharint register, if enabled through the spclchrinten bits. the spcharint interrupt is cleared when the isr is read. bit 0: lsrerrint the lsrerrint bit is set high when any lsr bits, which are enabled through the lsrinten, are set. this bit is cleared after the isr is read. address: 0x02 mode: cor bit 7 6 5 4 3 2 1 0 name ctsint rfifoemptyint tfifoemptyint tfifotrigint rfifotrigint stsint spcharint lsrerrint reset 0 1 1 0 0 0 0 0
max14830 quad serial uart with 128-word fifos and internal oscillator 33 lsrintenline status interrupt enable register the lsr interrupt enable register allows routing of lsr interrupt bits to the isr[0]. bits 7, 6: no function bit 5: noiseinten set the noiseinten bit high to enable routing the rxnoise interrupt to lsr[0]. if noiseinten is set low, rxnoise is not routed to lsr[0]. bit 4: rbreakien set the rbreakien bit high to enable routing the rxbreak interrupt to lsr[0]. if rbreakien is set low, rxbreak is not routed to lsr[0]. bit 3: frameerrien set the frameerrien bit high to enable routing the frameerr interrupt to lsr[0]. if frameerrien is set low, frameerr is not routed to lsr[0]. bit 2: parityien set the parityien bit high to enable routing the rxparityerr interrupt to lsr[0]. if parityien is set low, rxparityerr is not routed to the lsr[0]. bit 1: roverrien set the roverrien bit high to enable routing the rxoverrun interrupt to lsr[0]. if roverrien is set low, rxoverrun is not routed to lsr[0]. bit 0: rtimoutien set the rtimoutien bit high to enable routing the rtimeout interrupt to lsr[0]. if rtimoutien is set low, the rtimeout is not routed to lsr[0]. address: 0x03 mode: r/w bit 7 6 5 4 3 2 1 0 name noiseinten rbreakien frameerrien parityien roverrien rtimoutien reset 0 0 0 0 0 0 0 0
max14830 quad serial uart with 128-word fifos and internal oscillator 34 lsrline status register the line status register shows all errors related to the oldest word in the rxfifo waiting to be read out of the rhr. the lsr bits are not cleared upon a read; these bits stay set until the character with errors is read out of the rhr. the lsr also reflects the current state of the cts_ input. bit 7: ctsbit the cts bit reflects the current logic state of the cts_ input. this bit is cleared when the cts_ input is low. following a power-up or reset, the logic state of cts bit depends on the input of the cts_ input. bit 6: no function bit 5: rxnoise if noise is detected on the rx_ input during reception of a character, the rxnoise bit is set for that character. the rxnoise bit indicates that there was noise on the line while the current character residing in the rhr was received. rxnoise is cleared when the noisy character in the rhr is read out. the rxnoise flag can generate an isr[0] inter - rupt, if enabled through lsrinten[5]. bit 4: rxbreak if a line break (rx_ input low for a period longer than the programmed character duration) is detected, a break character is put in the rxfifo and the rxbreak bit is set for this character. a break character is represented by an all-zeros data character. the rxbreak bit distinguishes a regular character with all zeros from a break character. lsr[4] corresponds to the current character in the rhr. rxbreak is cleared when the break character is read out of the rhr. the rxbreak flag can generate an isr[0] interrupt if enabled through lsrinten[4]. bit 3: frameerr the frameerr bit is set high when the received data frame does not match the expected frame format in length. lsr[3] corresponds to the frame error of the current character in the rhr. a frame error is related to errors in expected stop bits. this error is cleared when the affected character is read out of the rhr. the frameerr flag can generate an isr[0] interrupt, if enabled, through lsrinten[3]. bit 2: rxparityerr if the parity computed on the character being received does not match the received characters parity bit, the rxparityerr bit is set for that character. lsr[2] indicates a parity error for the current word residing in the rhr. the lsr[2] bit is cleared when the affected character is read out of the rhr. in 9-bit multidrop mode (mode2[6] = 1) the receiver does not check parity and the lsr[2] represents the 9th (i.e. address or data) bit. the rxparityerr flag can generate an isr[0] interrupt, if enabled through lsrinten[2]. bit 1: rxoverrun if the receive fifo is full and additional data is received that does not fit into the receive fifo, the lsr[1] bit is set. the receive fifo retains the data in it and discards all new data that does not fit into it. the rxoverrun indication is cleared after the lsr is read or the rxfifo level falls below its maximum. the rxoverrun flag can generate an isr[0] interrupt, if enabled through lsrinten[1]. address: 0x04 mode: r bit 7 6 5 4 3 2 1 0 name ctsbit rxnoise rxbreak frameerr rxparityerr rxoverrun rtimeout reset x 0 0 0 0 0 0 0
max14830 quad serial uart with 128-word fifos and internal oscillator 35 bit 0: rtimeout the rtimeout bit indicates that stale data is present in the receive fifo. rtimeout is set when the youngest character resides in the rxfifo for longer than the period programmed into the rxtimeout register. the timeout counter restarts when at least one character is read out of the rxfifo or a new character is received by the rxfifo. if the value in rxtimeout is zero, lsr[0]: rtimeout is disabled. rtimeout is cleared when a word is read out of the rxfifo or a new word is received. the rtimeout flag can generate an isr[0] interrupt, if enabled through lsrinten[0]. spclchrintenspecial character interrupt enable register bits 7, 6: no function bit 5: mltdrpinten the mltdrpinten bit enables routing the spclcharint[5]: multidropint interrupt to isr[1]. if mltdrpinten is set low (default), the multidropint is not routed to the isr[1]. bit 4: breakinten the breakinten bit enables routing the spclcharint[4]: breakint interrupt to isr[1]. if breakinten is set low (default), the breakint is not routed to the isr[1]. bit 3: xoff2inten the xoff2inten bit enables routing the spclcharint[3]: xoff2int interrupt to isr[1]. if xoff2inten is set low (default), the xoff2int is not routed to the isr[1]. bit 2: xoff1inten the xoff1inten bit enables routing the spclcharint[2]: xoff1int interrupt to isr[1]. if xoff1inten is set low (default), the xoff1int is not routed to the isr[1]. bit 1: xon2inten the xon2inten bit enables routing the spclcharint[1]: xon2int interrupt to isr[1]. if xon2inten is set low (default), the xon2int is not routed to the isr[1]. bit 0: xon1inten the xon1inten bit enables routing the spclcharint[0]: xon1int interrupt to isr[1]. if xon1inten is set low (default), the xon1int is not routed to the isr[1]. address: 0x05 mode: r/w bit 7 6 5 4 3 2 1 0 name mltdrpinten breakinten xoff2inten xoff1inten xon2inten xon1inten reset 0 0 0 0 0 0 0 0
max14830 quad serial uart with 128-word fifos and internal oscillator 36 spclcharintspecial character interrupt register bits 7, 6: no function bit 5: multidropint the multidropint interrupt is set when the max14830 receives an address character in 9-bit multidrop mode (mode2[6] = 1). this bit is cleared when spclcharint is read. the multidropint bit can be routed to isr[1] by enabling spclchrinten[5]. bit 4: breakint the breakint interrupt is set when a line break (rx_ low for longer than one character length) is detected by the receiver. this bit is cleared after spclcharint is read. the breakint interrupt can be routed to isr[1] by enabling spclchrinten[4]. bit 3: xoff2int the xoff2int interrupt bit is set when an xoff2 special character is received and special character detection is enabled through mode2[4]. this interrupt is cleared upon reading spclcharint. the xoff2int interrupt can be routed to the isr[1] interrupt bit, if enabled through spclchrinten[3]. bit 2: xoff1int the xoff1int interrupt bit is set when an xoff1 special character is received and special character detection is enabled through mode2[4]. this interrupt is cleared upon reading spclcharint. the xoff1int interrupt can be routed to the isr[1] interrupt bit, if enabled through spclchrinten[2]. bit 1: xon2int the xon2int interrupt bit is set when an xon2 special character is received and special character detection is enabled through mode2[4]. this interrupt is cleared upon reading spclcharint. the xon2int interrupt can be routed to the isr[1] interrupt bit, if enabled through spclchrinten[1]. bit 0: xon1int the xon1int interrupt bit is set when an xon1 special character is received and special character detection is enabled through mode2[4]. this interrupt is cleared upon reading spclcharint. the xon1int interrupt can be routed to the isr[1] interrupt bit, if enabled through spclchrinten[0]. address: 0x06 mode: cor bit 7 6 5 4 3 2 1 0 name multidropint breakint xoff2int xoff1int xon2int xon1int reset 0 0 0 0 0 0 0 0
max14830 quad serial uart with 128-word fifos and internal oscillator 37 stsintensts interrupt enable register bits 7, 6: no function bit 5: clkrdyinten set the clkrdyinten bit high to route the clockready status bit to the isr[2]: stsint bit. if set low, the stsinten[5] masks the isr[2] bit from the clockready status. bit 4: no function bits 3C0: gpi[n]inten each uart has four individually assigned gpio outputs as follows: uart0: gpio0Cgpio3, uart1: gpio4Cgpio7, uart2: gpio8Cgpio11, uart3: gpio12Cgpio15. for example, for uart0: bit 0 is gpi0inten, bit 1 is gpi1inten, bit 2 is gpi2inten, and bit 3 is gpi3inten. see table 1. the gpi[n]inten bits that are set high route the associated stsint[3:0]: gpi[n]int bits to the isr[2] interrupt. gpi[n]inten bits that are set low, mask the isr[2] interrupt from the associated gpi[n]int bit. address: 0x07 mode: r/w bit 7 6 5 4 3 2 1 0 name clockrdyinten gpi3inten gpi2inten gpi1inten gpi0inten reset 0 0 0 0 0 0 0 0
max14830 quad serial uart with 128-word fifos and internal oscillator 38 stsintstatus interrupt register bits 7, 6: no function bit 5: clockready the clockready bit is set high when the clock, the divider, and pll have settled and the max14830 is ready for data communication. the clockready bit only works with the internal oscillator or the crystal oscillator. it does not work with external clocking through xin. the clockready status bit is cleared when the clock is disabled and is not cleared upon read. this bit can generate an isr[2]: stsint interrupt, if enabled through stsinten[5]. bit 4: no function bits 3C0: gpi[n]int each uart has four individually assigned gpio outputs as follows: uart0: gpio0Cgpio3, uart1: gpio4Cgpio7, uart2: gpio8Cgpio11, uart3: gpio12Cgpio15. for example, for uart0: bit 0 is gpi0int, bit 1 is gpi1int, bit 2 is gpi2int, and bit 3 is gpi3int. see table 1. the gpi[n]int interrupts are set high when a change of logic state occurs on the associated gpio_ input. gpi[n]int is cleared upon reading. these interrupts can be selectively routed to the isr[2] interrupt bit through the stsinten[3:0]. table 1. uart gpio assignments for gpio interrupts address: 0x08 mode: r/cor bit 7 6 5 4 3 2 1 0 name clockready gpi3int gpi2int gpi1int gpi0int reset 0 0 0 0 0 0 0 0 uart gpi3int/gpi3inten gpi2int/gpi2inten gpi1int/gpi1inten gpi0int/gpi0inten uart0 gpio3 gpio2 gpio1 gpio0 uart1 gpio7 gpio6 gpio5 gpio4 uart2 gpio11 gpio10 gpio9 gpio8 uart3 gpio15 gpio14 gpio13 gpio12
max14830 quad serial uart with 128-word fifos and internal oscillator 39 mode1 register bit 7: irqsel depending on the logic level of the irqsel bit, irq has different meanings. after a hardware or software (mode2[0]) reset, the irqsel bit is set low and, after a short delay, the irq output signals the end of the power-up sequence. the irq is low during power-up and transitions to high when the max14830 is ready to be programmed. irqsel can then be set high. in this case, irq becomes a regular interrupt output that signals pending interrupts, as indicated in the isr. details of the irqsel are described in the power-up and irq section. bits 6, 5: no function bit 4: trnscvctrl this bit enables the automatic transceiver direction control. set trnscvctrl high so that rts_ automatically controls the transceivers transmit/receive enable/disable inputs. setting trnscvctrl high sets rts_ low so that the transceiver is in receive mode. when the txfifo contains data available for transmission, the auto direction control sets rts_ high before the transmitter sends out the data. when the transmitter is empty, rts_ is automatically forced low again. setup and hold times of rts_ with respect to the tx_ output can be defined through the hdplxdelay register. a trans- mitter empty interrupt isr[5] is generated when the transmitter is empty. bit 3: rtshiz set the rtshiz bit high to three-state rts_. bit 2: txhiz set the txhiz bit high to three-state the tx_ output. bit 1: txdisabl set the txdisabl bit high to disable transmission. if the txdisabl bit is set high during transmission, the transmitter com - pletes sending out the current character and then ceases transmission. data still present in the transmit fifo remains in the txfifo. the tx_ output is set to logic-high after transmission. in auto transmitter disable mode, txdisabl is high when the transmitter is completely empty. bit 0: rxdisabl set the rxdisabl bit high to disable the receiver of the selected uart so that the receiver stops receiving data. all data present in the receive fifo remains in the rxfifo. address: 0x09 mode: r/w bit 7 6 5 4 3 2 1 0 name irqsel trnscvctrl rtshiz txhiz txdisabl rxdisabl reset 0 0 0 0 0 0 0 0
max14830 quad serial uart with 128-word fifos and internal oscillator 40 mode2 register bit 7: echosuprs set the echosuprs bit high so that the receiver (rx_) gates any data it receives when its transmitter is busy transmitting. in half-duplex communication (like irda and rs-485) this allows blocking of the locally echoed data. the receiver can block data for an extended time after the transmitter ceases transmission by programming a hold time in hdplxdelay[3:0] bits. bit 6: multidrop set the multidrop bit high to enable the 9-bit multidrop mode. if this bit is set, parity checking is not performed by the receiver and parity generation is not done by the transmitter. the parity error bit, lsr[2], has a different meaning in this case. the parity error bit represents the 9th bit (address/data indication) that is received with each 9-bit character. bit 5: loopback set the loopback bit high to enable internal local loopback mode. this internally connects tx_ to rx_ and also rts_ to cts_ . in local loopback mode, the tx_ output and the rx_ input are disconnected from the internal transmitter and receiver. the tx_ output is in three-state. the rts_ output remains connected to the internal logic and reflects the logic state programmed in lcr[7]. the cts_ input is disconnected from rts_ and the internal logic. cts_ thus remains in a high-impedance state. bit 4: specialchr the specialchr bit enables special character detection. the receiver can detect up to four special characters, as selected in flowctrl[5:4] and defined in the xon1, xon2, xoff1 and/or xoff2 registers, possibly in combination with gpio_ inputs, enabled through flowctrl[2]: gpiaddr. when a special character is received it is put into the rxfifo and a special character detect interrupt isr[1] is generated. special character detection can be used in addition to auto xon/xoff flow control, if enabled through flowctrl[3]. in this case xon/xoff flow control is then limited to single character xon and xoff and only two special characters can then be defined (in xon2 and xoff2). bit 3: rxemtyinv the rxemtyinv bit inverts the meaning of the receiver empty interrupt: isr[6]: rfifoemptyint. if rxemtyinv is set low (default state), the isr[6] interrupt is generated when the receive fifo is empty. if the rxemtyinv is set high, the isr[6] interrupt is generated when the receive fifo contains at least one character (i.e. is not empty). bit 2: rxtriginv the rxtriginv bit inverts the meaning of the rxfifo triggering. when set, an isr[3]: rfifotrigint is generated when the rxfifo is emptied to the trigger level: fifotrglvl[7:4]. if the rxtrginv bit is low (default state), the isr[3] interrupt is generated when the rxfifo fill level, which starts from a level below fifotrglvl[7:4], is filled up to the trigger level programmed into fifotrglvl[7:4]. bit 1: fiforst set the fiforst bit high to clear both the receive and transmit fifos of all data contents. after the fifo reset, the fiforst bit must then be set back to 0 to continue normal operation. bit 0: rst set the rst bit high to reset the selected uart in the max14830. the spi/i 2 c bus stays active during this reset and communication with the max14830 is possible. all register bits in the selected uart are reset to their reset state and the fifos are cleared during a reset. the global registers are not reset when the rst bit for a given uart is set. once set high, the rst bit must be cleared by writing a 0 to rst. address: 0x0a mode: r/w bit 7 6 5 4 3 2 1 0 name echosuprs multidrop loopback specialchr rxemtyinv rxtriginv fiforst rst reset 0 0 0 0 0 0 0 0
max14830 quad serial uart with 128-word fifos and internal oscillator 41 lcrline control register bit 7: rtsbit the rts bit provides direct control of the rts_ output logic. if rts bit is set to 1, then rts_ is set to logic-high. the rts bit only works when clksource[7]: clktorts is set to 0. bit 6: txbreak set txbreak to 1 to generate a line break whereby the tx_ output is held low. tx_ output remains low until txbreak is set to 0. bit 5: forceparity the forceparity bit enables forced parity, as used in 9-bit multidrop communication. set both lcr[3]: parityen and forceparity to 1 to use forced parity. the parity bit is forced high by the transmitter if lcr[4]: evenparity is low. the parity bit is forced low if the evenparity bit is high. bit 4: evenparity set the evenparity bit to 1 to generate even parity by the transmitter and parity is checked by the receiver. odd parity generation and checking are used if evenparity is set low. bit 3: parityen the parityen bit enables the use of a parity bit on the tx_ and rx_ interfaces. set the parityen bit to 0 to disable parity usage. when the parityen bit is 1, the transmitter generates the parity bit as defined in lcr[4], and the receiver checks the parity bit. bit 2: stopbits this defines the number of stop bits and depen ds on the length of the word programmed in lcr[1:0] (table 2). when lcr[2] is high and the word length is 5, the transmitter generates a word with a stop bit length equal to 1.5. under these conditions, the receiver recognizes a stop bit length greater than a 1-bit duration. bits 1, 0: length[n] the length[n] bits configure the length of the words that the transmitter generates and the receiver checks for at the asynchronous tx_ and rx_ interfaces (table 3). table 2. stopbits truth table table 3. length_ truth table address: 0x0b mode: r/w bit 7 6 5 4 3 2 1 0 name rtsbit txbreak forceparity evenparity parityen stopbits length1 length0 reset 0 0 0 0 0 1 0 1 stopbits bit word length stop bit length 0 5, 6, 7, 8 1 1 5 1C1.5 1 6, 7, 8 2 length1 length0 word length 0 0 5 0 1 6 1 0 7 1 1 8
max14830 quad serial uart with 128-word fifos and internal oscillator 42 rxtimeoutreceiver timeout register bits 7C0: timout[n] the receive data timeout bits allow programming a time delay after the last (newest) character in the receive fifo was received until a receive data timeout lsr[0] interrupt is generated. the duration is measured in character intervals and is dependent on the character length, parity, and stop bit setting and is inversely proportional to the baud rate. if the rxtimeout value equals zero, a timeout interrupt is not generated. hdplxdelay register the hdplxdelay register allows programming setup and hold times between rts_ and the tx_ output in automatic transceiver direction control mode (mode1[4] = 1). the hold[3:0] time can also be used for echo suppression in half- duplex communication. hdplxdelay also functions in the 2x and 4x rate modes. bits 7C4: setup[n] the setup[n] bits define a setup time for rts_ to transition high before the transmitter starts transmission of its first character in auto transceiver direction control mode: mode1[4]. this allows the max14830 to account for skew differ - ences of the external transmitters enable delay and propagation delays. setup[n] bits can also be used to fix a stable state on the transmission line prior to start of transmission. the unit of the hdplxdelay setup time delay is one bit interval, making this delay baud-rate dependent. the maximum delay is 15-bit intervals. bits 3C0: hold[n] the hold[n] bits define a hold time for rts_ to be held stable (high) after the transmitter ends transmission of its last character in auto transceiver direction control mode: mode1[4]. rts_ turns low after the last stop bit was sent with a hold[n] delay. this keeps the external transmitter enabled during the hold duration. the second factor that the hold[n] bits define is a delay in echo suppression mode, mode2[7]. see the echo suppression section for more information. the unit of the hdplxdelay hold time delay is one bit interval, making the delay baud-rate dependent. the maximum delay is 15-bit intervals. address: 0x0c mode: r/w bit 7 6 5 4 3 2 1 0 name timout7 timout6 timout5 timout4 timout3 timout2 timout1 timout0 reset 0 0 0 0 0 0 0 0 address: 0x0d mode: r/w bit 7 6 5 4 3 2 1 0 name setup3 setup2 setup1 setup0 hold3 hold2 hold1 hold0 reset 0 0 0 0 0 0 0 0
max14830 quad serial uart with 128-word fifos and internal oscillator 43 irda register the irda register allows selection of irda sir- and mir-compliant pulse shaping at the tx_ and rx_ interfaces. it also allows inversion of the tx_ and rx_ logic, independently of whether irda is enabled or not. bits 7, 6: no function bit 5: txinv set the txinv bit high to invert the logic at the tx_ output. this is independent of irda operation. bit 4: rxinv set the rxinv bit high to invert the logic state at the rx_ input. this is independent of irda operation. bit 3: mir set the mir and irdaen bits high to select irda 1.1 (mir) with 1/4 period pulse widths. bit 2: shortir set the shortir and irdaen bits high to select irda 1.0 (sir) with the transmitter producing the minimum allowed pulse widths of 1.63 fs. bit 1: sir set the sir bit and the irdaen bits high to select irda 1.0 pulses (sir) with 3/16th period pulses. bit 0: irdaen set the irdaen bit high so that irda compliant pulses are produced at the tx_ output and the max14830 receiver expects such pulses at its rx input. if irda[0] is set to low (default), normal (non-irda) pulses are generated and expected at the receiver. irdaen must be used in conjunction with the sir, shortir, or mir select bits. address: 0x0e mode: r/w bit 7 6 5 4 3 2 1 0 name txinv rxinv mir shortir sir irdaen reset 0 0 0 0 0 0 0 0
max14830 quad serial uart with 128-word fifos and internal oscillator 44 flowlvlflow level register flowlvl is used for selecting the rxfifo threshold levels used for software (xon/xoff) and hardware (rts/cts) flow control. bits 7C4: resume[n] resume[n] bits set the transmit fifo threshold at which an xon is automatically sent or rts_ is automatically set low. this signals the far end station to start transmission. the actual threshold level is calculated as 8 x resume[n]. the resulting level is in the range of 0 to 120. bits 3C0: halt[n] halt[n] bits set a receive fifo threshold level at which an xoff is automatically sent or rts_ is automatically set high, depending on whether automatic software or hardware flow control is enabled. this signals the far end station to halt transmission. the actual threshold level is calculated as 8 x halt[n]. hence the selectable threshold granularity is eight. the resulting level is in the range of 0 to 120. fifotriglvlfifo interrupt trigger level register bits 7C4: rxtrig[n] the rxtrig[n] bits allow definition of the receive fifo threshold level at which an isr[3] interrupt is generated. this can be used to signal that the receive fifo is nearing overflow or that a predefined number of fifo locations are available for being read out in one block. the actual fifo trigger level is 8 x rxtrig[n], hence the selectable threshold granularity is eight. bits 3C0: txtrig[n] the txtrig[n] bits allow definition of the transmit fifo threshold level at which the max14830 generates an isr[4] interrupt. this can be used to manage data flow to the transmit fifo. for example, if the trigger level is defined near the bottom of the txfifo, the host knows that a predefined number of fifo locations are available to be written to in one block. alternatively, if the trigger level is set near the top of the fifo, the host is warned when the transmit fifo is nearing overflow, if written to on a word-by-word basis. the actual fifo trigger level is 8 x txtrig[n], hence the selectable threshold granularity is eight. address: 0x0f mode: r/w bit 7 6 5 4 3 2 1 0 name resume3 resume2 resume1 resume0 halt3 halt2 halt1 halt0 reset 0 0 0 0 0 0 0 0 address: 0x10 mode: r/w bit 7 6 5 4 3 2 1 0 name rxtrig3 rxtrig2 rxtrig1 rxtrig0 txtrig3 txtrig2 txtrig1 txtrig0 reset 1 1 1 1 1 1 1 1
max14830 quad serial uart with 128-word fifos and internal oscillator 45 txfifolvltransmit fifo level register bits 7C0: txfl[n] the txfifolvl register represents the current number of words in the transmit fifo. rxfifolvlreceive fifo level register bits 7C0: rxfl[n] the rxfifolvl level register represents the current number of words in the receive fifo. flowctrlflow control register bits 7C4: swflow[n] the swflow[n] bits configure auto software flow control and/or special character detection in combination with the characters defined in the xon1, xon2, xoff1, and/or xoff2 registers. see table 4. flowctrl[n] select which of the xon1, xon2, xoff1, or/and xoff2 characters are used for special character detec - tion and/or auto flow control. if auto receiver flow control is enabled through swflowen and flowctrl[n], the xon and xoff characters that the max14830 receives are filtered out and are not put into the rxfifo. set the swflowen bit to 0 and set mode2[4] to 1 to enable special character detection. under these conditions, auto flow transmit flow control is not used. if both special character detection (mode2[4]) and automatic software flow control (flowctrl[3]) are to be enabled, xon1 and xoff1 define the auto flow control characters while xon2 and xoff2 define the special character detec - tion characters. bit 3: swflowen the swflowen bit enables automatic software flow control. the characters used for automatic software flow control are selected in flowctrl[n]. if special character detection (mode2[4] = 1) is used in addition to automatic software flow control, xon1 and xoff1 are used for flow control, while xon2 and xoff2 define the special characters. address: 0x11 mode: r bit 7 6 5 4 3 2 1 0 name txfl7 txfl6 txfl5 txfl4 txfl3 txfl2 txfl1 txfl0 reset 0 0 0 0 0 0 0 0 address: 0x12 mode: r bit 7 6 5 4 3 2 1 0 name rxfl7 rxfl6 rxfl5 rxfl4 rxfl3 rxfl2 rxfl1 rxfl0 reset 0 0 0 0 0 0 0 0 address: 0x13 mode: r/w bit 7 6 5 4 3 2 1 0 name swflow3 swflow2 swflow1 swflow0 swflowen gpiaddr autocts autorts reset 0 0 0 0 0 0 0 0
max14830 quad serial uart with 128-word fifos and internal oscillator 46 bit 2: gpiaddr the gpiaddr bit, when set, enables that the four gpio_ inputs are used in conjunction with xoff2 for the definition of a special character. this can be used, for example, for defining the address of a rs-485 slave device through hard - ware. the gpio_ input logic levels define the four lsbs of the special character, while the four msbs are defined by the xoff2[7:4] bits. if gpiaddr is set, the contents of the xoff2[3:0] bits are neglected. in this case, the xoff2[3:0] bits, when read, also do not reflect the logic on gpio_. bit 1: autocts the autocts bit enables automatic cts flow control by which the transmitter stops and starts sending data depend - ing on the logic state at the cts_ input. see the auto hardware flow control section for a description of autocts flow control. logic changes at the cts_ input result in an isr[7]: ctsint interrupt. the transmitter must be turned off, (mode1[1] = 1), before autocts is enabled. bit 0: autorts the autorts bit enables automatic rts flow control by which the max14830 sets its rts_ output dependent on the receive fifo fill level. the fifo thresholds at which rts_ changes state are set in flowlvl. see the auto hardware flow control section for more information. table 4. swflow_ truth table x = dont care. swflow3 swflow2 swflow1 swflow0 description receiver flow control transmitter flow control/special character detection 0 0 0 0 no flow control. no character detection. 0 0 x x no receiver flow control. 1 0 x x transmitter generates xon1, xoff1. 0 1 x x transmitter generates xon2, xoff2. 1 1 x x transmitter generates xon1, xon2, xoff1, and xoff2. x x 0 0 no transmitter flow control. x x 1 0 receiver compares xon1 and xoff1 and controls the transmitter accord - ingly. xon1 and xoff1 special character detection. x x 0 1 receiver compares xon2 and xoff2 and controls the transmitter accord - ingly. xon2 and xoff2 special character detection. x x 1 1 receiver compares xon1, xon2, xoff1, and xoff2 and controls the transmitter accordingly. xon1, xon2, xoff1, xoff2 special character detection.
max14830 quad serial uart with 128-word fifos and internal oscillator 47 xon1 register the xon1 and xon2 register contents define the xon characters used for automatic xon/xoff flow control and/or the special characters used for special character detection. see details in the flowctrl register description. bits 7C0: bit[n] these bits define the xon1 character if single character xon auto software flow control is enabled in flowcntrl[7:4]. if double character flow control is selected in flowcntrl[7:4], these bits constitute the lsb of the xon character. if special character detection is enabled in mode2[4] and auto flow control is not enabled, these bits define a special character. if special character detection and auto software flow control are enabled, xon1 defines the xon flow control character. xon2 register the xon1 and xon2 register contents define the xon characters for automatic xon/xoff flow control and/or the special characters used in special character detection. see details in the flowctrl register description. bits 7C0: bit[n] these bits define the xon2 character if single character auto software flow control is enabled in flowcntrl[7:4]. if double character flow control is selected in flowcntrl[7:4], these bits constitute the msb of the xon character. if special character detection is enabled in mode2[4] and auto software flow control is not enabled, these bits define a special character. if both special character detection and auto flow control are enabled (mode2[4] and flowcntrl[3]), these bits define a special character. address: 0x14 mode: r/w bit 7 6 5 4 3 2 1 0 name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reset 0 0 0 0 0 0 0 0 address: 0x15 mode: r/w bit 7 6 5 4 3 2 1 0 name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reset 0 0 0 0 0 0 0 0
max14830 quad serial uart with 128-word fifos and internal oscillator 48 xoff1 register the xoff1 and xoff2 register contents define the xoff characters for automatic xon/xoff flow control and/or the special characters used in special character detection. see details in the flowctrl register description. bits 7C0: bit[n] these bits define the xoff1 character if single character xoff auto software flow control is enabled in flowcntrl[7:4]. if double character flow control is selected in flowcntrl[7:4], these bits constitute the lsb of the xoff character. if special character detection is enabled in mode2[4] and auto software flow control is not enabled, these bits define a special character. if special character detection and software flow control area both enabled, xoff1 defines the xoff flow control character. xoff2 register the xoff1 and xoff2 register contents define the xoff characters for automatic xon/xoff flow control and/or spe - cial characters used for special character detection. see details in the flowctrl register description. bits 7C0: bit[n] these bits define the xoff2 character if auto software flow control is enabled in flowcntrl[7:4]. if double character flow control is selected in flowcntrl[7:4], these bits constitute the msb of the xoff character. if special character detection is enabled in mode2[4] and auto flow control is not enabled, these bits define a special character. if both special char - acter detection and auto flow control are enabled (mode2[4] and flowcntrl[3]), these bits define a special character. address: 0x16 mode: r/w bit 7 6 5 4 3 2 1 0 name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reset 0 0 0 0 0 0 0 0 address: 0x17 mode: r/w bit 7 6 5 4 3 2 1 0 name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reset 0 0 0 0 0 0 0 0
max14830 quad serial uart with 128-word fifos and internal oscillator 49 gpioconfggpio configuration register each uart has four gpios that can be configured as inputs or outputs and can be operated in push-pull or open-drain mode. the reference clock must be active for the gpios to work. bits 7C4: gp[n]od each uart has four individually assigned gpio outputs as follows: uart0: gpio0Cgpio3, uart1: gpio4Cgpio7, uart2: gpio8Cgpio11, uart3: gpio12Cgpio15. for example, for uart0: bit 4 is gp0od, bit 5 is gp1od, bit 6 is gp2od, and bit 7 is gp3od (see table 5). set gp[n]od bits to 0 to configure the gpio_s as push-pull outputs, if configured as outputs in gpioconfg[3:0]. set the gp[n]od bits to 1 to configure to open-drain output operation. when configured as inputs in gpioconfg[3:0], the gpio_s are high-impedance inputs with weak pulldowns. bits 3C0: gp[n]out each uart has four individually assigned gpio outputs as follows: uart0: gpio0Cgpio3, uart1: gpio4Cgpio7, uart2: gpio8Cgpio11, uart3: gpio12Cgpio15. for example, for uart0: bit 0 is gp0out, bit 1 is gp1out, bit 2 is gp2out, and bit 3 is gp3out (see table 5). the gp[n]out bits configure the gpio_ to be inputs or outputs. set the gp[n]out bits to 1 to configure the associated gpio_s as outputs. set the gp[n]out bits to 0 to configure the associated gpios as inputs. table 5. uart gpio assignments for gpio configuration address: 0x18 mode: r/w bit 7 6 5 4 3 2 1 0 name gp3od gp2od gp1od gp0od gp3out gp2out gp1out gp0out reset 0 0 0 0 0 0 0 0 uart gp3od/gp3out gp2od/gp2out gp1od/gp1out gp0od/gp0out uart0 gpio3 gpio2 gpio1 gpio0 uart1 gpio7 gpio6 gpio5 gpio4 uart2 gpio11 gpio10 gpio9 gpio8 uart3 gpio15 gpio14 gpio13 gpio12
max14830 quad serial uart with 128-word fifos and internal oscillator 50 gpiodatagpio data register bits 7C4: gpi[n]dat each uart has four individually assigned gpio outputs as follows: uart0: gpio0Cgpio3, uart1: gpio4Cgpio7, uart2: gpio8Cgpio11, uart3: gpio12Cgpio15. for example, for uart0: bit 4 is gpi0dat, bit 5 is gpi1dat, bit 6 is gpi2dat, and bit 7 is gpi3dat (see table 6). the gpi[n]dat bits reflect the logic on the gpio_s. bits 3C0: gpo[n]dat each uart has four individually assigned gpio outputs as follows: uart0: gpio0Cgpio3, uart1: gpio4Cgpio7, uart2: gpio8Cgpio11, uart3: gpio12Cgpio15. for example, for uart0: bit 0 is gpo0dat, bit 1 is gpo1dat, bit 2 is gpo2dat, and bit 3 is gpo3dat (see table 6). the gpo[n]dat bits allow programming the logic state of the gpio_, when configured as outputs in gpioconfg[3:0]. for open-drain operation, pullup resistors are needed on gpio_. table 6. uart gpio assignments for gpio input/output data address: 0x19 mode: r/w bit 7 6 5 4 3 2 1 0 name gpi3dat gpi2dat gpi1dat gpi0dat gpo3dat gpo2dat gpo1dat gpo0dat reset 0 0 0 0 0 0 0 0 uart gpi3dat/gpo3dat gpi2dat/gpo2dat gpi1dat/gpo1dat gpi0dat/gpo0dat uart0 gpio3 gpio2 gpio1 gpio0 uart1 gpio7 gpio6 gpio5 gpio4 uart2 gpio11 gpio10 gpio9 gpio8 uart3 gpio15 gpio14 gpio13 gpio12
max14830 quad serial uart with 128-word fifos and internal oscillator 51 pllconfigpll configuration register bits 7, 6: pllfactor[n] the pllfactor[n] bits allow programming with select pll multiplication factors. the input and output frequencies of the pll have to be limited to the ranges shown in table 7. enable the pll through clksource[2]. bits 5C0: prediv[n] the prediv[n] bits allow programming the divisor of the plls predivider. the divisor must be chosen so that the output frequency of the predivider, which equals the plls input frequency, is limited to the ranges shown in table 4. the output frequency of the internal oscillator, or the input frequency of xin, is f clk : f pllin = f clk /prediv see figure 17. prediv is an integer that must be in the range of 1 to 63. figure 17. pll signal path table 7. pllfactor_ selector guide address: 0x1a mode: r/w bit 7 6 5 4 3 2 1 0 name pllfactor1 pllfactor0 prediv5 prediv4 prediv3 prediv2 prediv1 prediv0 reset 0 0 0 0 0 0 0 1 f clk f pll in pll pre-divider f ref fractional baud-rate generators pllfactor1 pllfactor0 multiplication factor f pllin f ref min max min max 0 0 6 500khz 800khz 3mhz 4.8mhz 0 1 48 850khz 1.2mhz 40.8mhz 56mhz 1 0 96 425khz 1mhz 40.8mhz 96mhz 1 1 144 390khz 667khz 56mhz 96mhz
max14830 quad serial uart with 128-word fifos and internal oscillator 52 brgconfigbaud-rate generator configuration register bits 7, 6: no function bit 5: 4xmode when the 4xmode bit is set high, the max14830 baud rate is quadruple the regular (16x sampling) baud rate. the 2xmode bit should be set low if 4xmode is enabled. see the 2x and 4x rate modes section for more information. bit 4: 2xmode when the 2xmode bit is set high, the max14830 baud rate is double the regular (16x sampling) baud rate. see the 2x and 4x rate modes section for a detailed description. bits 3C0: fract[n] this is the fractional portion of the baud-rate generator divisor. set fract[n] to zero if not used. see the fractional baud-rate generator section for calculations. divlsbbaud-rate generator lsb divisor register divlsb and divmsb define the baud-rate generator integer divisors. the minimum value is 1. see the fractional baud- rate generator section for more information. bits 7C0: div[n] the divlsb register is the lsbs of the integer divisor portion (div) of the baud-rate generator. divmsbbaud-rate generator msb divisor register bits 7C0: div[n] the divmsb register is the msb portion of the integer divisor (div). address: 0x1b mode: r/w bit 7 6 5 4 3 2 1 0 name 4xmode 2xmode fract3 fract2 fract1 fract0 reset 0 0 0 0 0 0 0 0 address: 0x1c mode: r/w bit 7 6 5 4 3 2 1 0 name div7 div6 div5 div4 div3 div2 div1 div0 reset 0 0 0 0 0 0 0 1 address: 0x1d mode: r/w bit 7 6 5 4 3 2 1 0 name div15 div14 div13 div12 div11 div10 div9 div8 reset 0 0 0 0 0 0 0 0
max14830 quad serial uart with 128-word fifos and internal oscillator 53 clksourceclock source register bit 7: clktorts set the clktorts bit to 1 to route the baud-rate generator (16x baud rate) output clock to rts_ . the clock frequency is a factor of 16x, 8x, or 4x of the baud rate, depending on the brgconfig[5:4] settings. bits 6, 5: no function bit 4: extclock set the extclock bit to 1 to enable an external clocking source (crystal or clock generator at xin). set the extclock bit to 0 to select the internal oscillator for clocking. bit 3: pllbypass set the pllbypass bit to 1 to enable bypassing the internal pll and predivider. bit 2: pllen set the pllen bit to 1 to enable the internal pll. set pllen to 0 to disable the internal pll. bit 1: crystalen set the crystalen bit to 1 to enable the crystal oscillator. when using an external clock source at xin, set crystalen to 0. bit 0: intoscen set the intoscen bit to 1 to enable the internal oscillator. set intoscen to 0 to disable the internal oscillator. globalirqglobal irq register bits 7C4: no function bits 3C0: irq[n] the max14830 has a single irq output. the globalirq register bits report which of the uarts have an interrupt pend- ing, as enabled in the isrinten registers. the globalirq register can be read in two ways: either by reading register 0x1f of any of the four uarts or by sam - pling the 4 bits sent to the master on miso during the command byte of a read cycle (full-duplex spi) (see the fast read cycle section for more information). irq [n] is set to 1 when the associated uart's internal irq is generated. irq_ bits are cleared when the associated uart interrupt is cleared. uart interrupts are cleared by reading the uart isr register. address: 0x1e mode: r/w bit 7 6 5 4 3 2 1 0 name clktorts extclock pllbypass pllen crystalen intoscen reset 0 0 0 0 1 0 0 0 address: 0x1f mode: r bit 7 6 5 4 3 2 1 0 name irq3 irq2 irq1 irq0 reset 0 0 0 0 1 1 1 1
max14830 quad serial uart with 128-word fifos and internal oscillator 54 globlcomndglobal command register bits 7C0: glbcom[n] the globlcomnd register is the only global write register in the max14830. every byte written to globlcomnd is sent simultaneously to all four uarts. every byte sent by the spi/i 2 c master to location 0x1f is interpreted as a global com - mand by all the four internal uarts. the max14830 logic supports the following commands (table 8): ? global tx synchronization ? extended addressing space enable (to get access to registers beyond address 0x1f) ? extended addressing space disable (to disable access to registers beyond address 0x1f) the last two commands (0xce/0xcd) enable/disable the access to registers in the extended space of the register map when max14830 operates in spi mode. the spi command byte has only 5 bits to address a given register so that the registers beyond 0x1f could not be addressed using the standard access method. in i 2 c mode, there is no need to explicitly enable and disable the extended register map access as i 2 c allows up to 7 bits for register addressing. to extend the addressing capability of the spi command byte, send a 0xce to location 0x1f. the internal spi address is generated as 0010 a3a2a1a0, where a3a2a1a0 is the least significant nibble of the command byte. bit a4 of the command byte is disregarded when the extended space of the register map is enabled and only the least significant nibble is used for addressing purposes (table 9). bits u1 and u0 of the command byte maintain their meaning in the extended mode. see the spi interface section for more information. to return to standard addressing mode, the spi master has to send the 0xcd command. in this case, the internal spi address is generated as follows (default): 000a4 a3a2a1a0 table 8. globlcomnd command descriptions table 9. extended mode addressing (spi only) globlcomnd[7:0] command description 0xe0 tx command 0 0xe1 tx command 1 0xe2 tx command 2 0xe3 tx command 3 0xe4 tx command 4 0xe5 tx command 5 0xe6 tx command 6 0xe7 tx command 7 0xe8 tx command 8 0xe9 tx command 9 0xea tx command 10 0xeb tx command 11 0xec tx command 12 0xed tx command 13 0xee tx command 14 register spi mode address i 2 c mode address txsynch 0x00 0x20 synchdelay1 0x01 0x21 synchdelay2 0x02 0x22 timer1 0x03 0x23 timer2 0x04 0x24 revid 0x05 0x25 address: 0x1f mode: w bit 7 6 5 4 3 2 1 0 name glbco m7 glbcom6 glbcom5 glbcom4 glbcom3 glbcom2 glbcom1 glbcom0 globlcomnd[7:0] command description 0xef tx command 15 0xce enable extended register map access 0xcd disable extended register map access
max14830 quad serial uart with 128-word fifos and internal oscillator 55 txsynchtransmitter synchronization register the txsynch register is used to configure transmitter synchronization with a global spi or i 2 c command. one of 16 trigger commands (table 5) can be selected to be the synchronization trigger source for every uart. this allows simultaneous start of transmission of multiple uarts that are associated with the same global trigger command. the synchronized uarts can be on a single max14830 or on multiple devices if they are controlled by a common spi interface. uarts start transmission when a global trigger command is received. start of transmission is considered to be the falling edge of the start bit at the tx_ output. a delay can optionally be programmed through the synchdelay1 and synchdelay2 registers. tx synchronization is managed through software by transmitting the broadcast trigger tx command (table 5) to the max14830 through the spi or i 2 c interface. to selectively synchronize ports that are on the same max14830 (intrachip synchronization) or on different max14830 (interchip synchronization) devices, up to 16 trigger tx commands have been defined (see the globlcomnd section for more information) . bit 7: clktogpio the clktogpio bit is used to provide a buffered replica of the uarts system clock (i.e. the fractional divider input) to a gpio. the assignment is as follows: uart0s clock is routed to gpio0, uart1s clock is routed to gpio4, uart2s clock is routed to gpio8, and uart3s clock is routed to gpio12. bit 6: txautodis set the txautodis bit to 1 to enable automatic transmitter disabling. when txautodis is 1, the transmitter is automati - cally disabled when all data in the txfifo has been transmitted. after the transmitter is disabled, the txfifo can then be filled with data that is transmitted when its assigned trigger command, defined by the trigselx bits, is received. bit 5: trigdelay set trigdelay to 1 to enable delayed start of transmission. the uart starts transmitting data following a delay pro - grammed in synchdelay1 and synchdelay2 after receiving the assigned trigger command. bit 4: synchen set synchen to 1 to enable the software tx synchronization. when synchen is high, the uart starts transmitting data after receiving the expected trigger command, if the txfifo contains data. setting synchen high forces the txdisabl bit (mode1[1]) high and thereby disables the uarts transmitter. this prevents the transmitter from sending data as soon as the txfifo contains some. once the txfifo has been loaded, the uart starts transmitting data only upon receiving the assigned trigger command. set synchen to 0 to disable transmitter synchronization for that uart. when synchen is 0, that uarts transmitter does not start transmission through any trigger command. bits 3C0: trigsel[n] the trigsel[n] bits select the trigger command for that uarts transmitter synchronization when synchen is 1. for example, set txsynch[3:0] to 0x08 for the uart to be triggered by tx command 8 (0xe8, table 5). address: 0x20 mode: r/w bit 7 6 5 4 3 2 1 0 name clktogpio txautodis trigdelay synchen trigsel3 trigsel2 trigsel1 trigsel0 reset 0 0 0 0 0 0 0 0
max14830 quad serial uart with 128-word fifos and internal oscillator 56 synchdelay1synchronization delay register 1 the synchdelay1 and synchdelay2 register contents define the time delay between when the uart receives an assigned transmitter trigger command and when the uart begins transmission. bits 7C0: sdelay[n] sdelay[7:0] are the 8 lsbs of the delay between when the uart receives an assigned transmitter trigger command and when the uart begins transmission. the delay is expressed in number of uart bit intervals (1/baudrate). the maximum delay is 65,535-bit intervals. for example, given a baud rate of 230.4kbps and a bit time of 4.34 f s, the maximum delay is 284ms. synchdelay2synchronization delay register 2 the synchdelay1 and synchdelay2 register contents define the time delay between when the uart receives an assigned transmitter trigger command and when the uart begins transmission. bits 7C0: sdelay[n] sdelay[15:8] are the 8 msbs of the delay between when the uart receives an assigned transmitter trigger command and when the uart begins transmission. the delay is expressed in number of uart bit intervals (1/baudrate). the maximum delay is 65,535-bit intervals. for example, given a baud rate of 230.4kbps and a bit time of 4.34 f s, the maximum delay is 284ms. timer1timer register 1 the timer1 and timer2 register contents can be used to generate a low-frequency clock signal on a gpio_ output. the low-frequency clock is a divided replica of the fractional divider output. bits 7C0: timer[n] timer[7:0] are the 8 lsbs of the 15-bit timer divisor. see the timer2 register description. if timer1 and timer2 are both 0x00, the low-frequency clock is off. address: 0x21 mode: r/w bit 7 6 5 4 3 2 1 0 name sdelay7 sdelay6 sdelay5 sdelay4 sdelay3 sdelay2 sdelay1 sdelay0 reset 0 0 0 0 0 0 0 0 address: 0x22 mode: r/w bit 7 6 5 4 3 2 1 0 name sdelay15 sdelay14 sdelay13 sdelay12 sdelay11 sdelay10 sdelay9 sdelay8 reset 0 0 0 0 0 0 0 0 address: 0x23 mode: r/w bit 7 6 5 4 3 2 1 0 name timer7 timer6 timer5 timer4 timer3 timer2 timer1 timer0 reset 0 0 0 0 0 0 0 0
max14830 quad serial uart with 128-word fifos and internal oscillator 57 timer2timer register 2 the timer1 and timer2 register contents can be used to generate a low-frequency clock signal on a gpio_ output. the low-frequency clock is a divided replica of the fractional divider output. bit 7: tmrtogpio set tmrtogpio to 1 to enable clock generation at a gpio output. the clock signal is routed to a gpio output as fol - lows: uart0 clock signal to gpio1, uart1 clock signal to gpio5, uart2 clock signal to gpio9, uart3 clock signal to gpio13. the output clock has a 50% duty cycle. bits 6C0: timer[n] timer[14:8] are the 7 msbs of the 15-bit timer divisor. the clock frequency is calculated using the following formula: f timer_clk = uartclk/(1024 x timerx) where uartclk is the fractional baud-rate generator output (i.e. 16 x baudrate). when using 2x or 4x rate modes, uartclk is 8 x baudrate or 4 x baudrate, respectively. if timer1 and timer2 are both 0x00, the low-frequency clock is off. revidrevision identification register bits 7C0: bit[n] the revid register indicates the revision number of the max14830 siliconstarting with 0xb1. this can be used during software development as a known reference. address: 0x24 mode: r/w bit 7 6 5 4 3 2 1 0 name tmrtogpio timer14 timer13 timer12 timer11 timer10 timer9 timer8 reset 0 0 0 0 0 0 0 0 address: 0x25 mode: r bit 7 6 5 4 3 2 1 0 name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reset 1 0 1 1 0 0 0 1
max14830 quad serial uart with 128-word fifos and internal oscillator 58 serial controller interface the max14830 can be controlled through spi or i 2 c as defined by the logic on spi /i2c . see the pin configuration section for further details. spi interface the spi interface supports both single cycle and burst read/write access. the spi master must generate clock and data signals in spi mode0 (i.e. with clock polarity cpol = 0 and clock phase cpha = 0). each of the four uarts is addressed using 2 bits (u1 and u0) in the command byte (see tables 10 and 11). miso operation before a specific uart has been addressed, all four uarts can attempt to drive miso. to avoid this conten - tion, the miso line is held in high impedance during a write cycle (figure 18). during a read cycle, miso is high impedance for the first 4 clock cycles of the command byte. once the spi address (u1 and u0) has been properly decoded, the addressed spi drives the miso line (figure 19). spi burst access burst access allows writing and reading in one block, by only defining the initial register address in the spi command byte. multiple characters can be loaded into the txfifo by using the thr (0x00) as the initial burst write address. similarly, multiple characters can be read out of the rxfifo by using the rhr (0x00) as the spis burst read address. if the spi burst address is differ - ent to 0x00, the max14830 automatically increments the register address after each spi data byte. efficient programming of multiple consecutive registers is thus possible. chip select, cs /a0, must be kept low during the whole cycle. the sclk/scl clock continues clocking throughout the burst access cycle. the burst cycle ends when the spi master pulls cs /a0 high. for example, writing 128 bytes into a txfifo can be achieved by a burst write access through the following sequence: 1) pull cs /a0 low. 2) send spi write command. 3) send 128 bytes. 4) release cs/a0. this takes a total of (1 + 128) x 8 clock cycles. table 10. spi command byte configuration a[4:0] = register address figure 18. spi write cycle table 11. spi u1, u0 uart selection high-z ax = register address dx = eight-bit register contents cs sclk mosi miso w u 1 u0 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 spi command byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w/r u1 u0 a4 a3 a2 a1 a0 u1 u0 uart selected 0 0 uart0 0 1 uart1 1 0 uart2 1 1 uart3
max14830 quad serial uart with 128-word fifos and internal oscillator 59 fast read cycle on the max14830 the four uart interrupts share the single irq output. when operating in interrupt-based mode, the microcontroller needs to locate the source of the interrupt (i.e. which of the four uarts generated the interrupt) and clear the interrupt. to locate the source of an interrupt more quickly, the max14830 implements the spi fast read cycle. this means that the microcontroller can determine which uart is the source of the interrupt (uart0, uart1, uart2, or uart3) using only 8 clock cycles (figure 20). u1 and u0 bits are ignored during the fast read cycle. i 2 c interface the max14830 contains an i 2 c-compatible interface for data communication with a host processor (scl and sda). the interface supports a clock frequency up to 1mhz. scl and sda require pullup resistors that are connected to a positive supply. start, stop, and repeated start conditions when writing to the max14830 using i 2 c, the master sends a start condition (s) followed by the max14830 i 2 c address. after the address, the master sends the register address of the register that is to be pro - grammed. the master then ends communication by figure 19. spi read cycle figure 20. spi fast read cycle high-z ax = register address dx = eight-bit register contents sclk mosi miso r u1 u0 a4 a3 a2 a1 a0 cs irq3 irq2 irq1 irq0 d7 d6 d5 d4 d3 d2 d1 d0 mosi ax = register address sclk cs miso u1 high-z r u0 a4 a3 a2 a1 a0 irq3 irq2 irq1 irq0
max14830 quad serial uart with 128-word fifos and internal oscillator 60 issuing a stop condition (p), to relinquish control of the bus, or a repeated start condition (sr) to communi - cate to another i 2 c slave. see figure 21. slave address the max14830 includes a 7-bit i 2 c slave address, allow - ing up to 16 max14830 devices to share the same i 2 c bus. the first 5 bits (msbs) of the slave address are factory programmed and are predefined for each of the four uarts (uart0, uart1, uart2, and uart3). the two lsbs of the address are defined by connecting the mosi/a1 and cs /a0 inputs to ground, v l , sda or to scl (table 12). set the read/write bit to 1 to configure the max14830 to read mode. set the read/write bit to 0 to configure the max14830 to write mode. the address is the first byte of information sent to the max14830 after the start condition. figure 21. i 2 c start, stop and repeated start conditions table 12. i 2 c address map scl sda s sr p mosi/a1 cs/a0 uart0 uart1 uart2 uart3 write read write read write read write read dgnd dgnd 0xd8 0xd9 0xb8 0xb9 0x58 0x59 0x38 0x39 dgnd v l 0xc2 0xc3 0xa2 0xa3 0x42 0x43 0x22 0x23 dgnd scl 0xc4 0xc5 0xa4 0xa5 0x44 0x45 0x24 0x25 dgnd sda 0xc6 0xc7 0xa6 0xa7 0x46 0x47 0x26 0x27 v l dgnd 0xc8 0xc9 0xa8 0xa9 0x48 0x49 0x28 0x29 v l v l 0xca 0xcb 0xaa 0xab 0x4a 0x4b 0x2a 0x2b v l scl 0xcc 0xcd 0xac 0xad 0x4c 0x4d 0x2c 0x2d v l sda 0xce 0xcf 0xae 0xaf 0x4e 0x4f 0x2e 0x2f scl dgnd 0xd0 0xd1 0xb0 0xb1 0x50 0x51 0x30 0x39 scl v l 0xd2 0xd3 0xb2 0xb3 0x52 0x53 0x32 0x39 scl scl 0xd4 0xd5 0xb4 0xb5 0x54 0x55 0x34 0x39 scl sda 0xd6 0xd7 0xb6 0xb7 0x56 0x57 0x36 0x39 sda dgnd 0xc0 0xc1 0xa0 0xa1 0x40 0x41 0x20 0x21 sda v l 0xda 0xdb 0xba 0xbb 0x5a 0x5b 0x3a 0x3b sda scl 0xdc 0xdd 0xbc 0xbd 0x5c 0x5d 0x3c 0x3d sda sda 0xde 0xdf 0xbe 0xbf 0x5e 0x5f 0x3e 0x3f
max14830 quad serial uart with 128-word fifos and internal oscillator 61 bit transfer one data bit is transferred during each scl clock cycle. the data on sda must remain stable during the high period of the scl clock pulse. changes in sda while scl is high and stable are considered control signals (see the start, stop, and repeated start conditions section). both sda and scl remain high when the bus is not active. single-byte write with this operation the master sends an address and one or two data bytes to the slave device (figure 22). the write byte procedure is the following: 1) the master sends a start condition. 2) the master sends the 7-bit slave id plus a write bit (low). 3) the addressed slave asserts an ack on the data line. 4) the master sends the 8-bit register address. 5) the active slave asserts an ack on the data line only if the address is valid (nak if not). 6) the master sends an 8-bit data byte. 7) the slave asserts an ack on the data line. 8) the master generates a stop condition. burst write with this operation the master sends an address and multiple data bytes to the slave device (figure 23). the burst write procedure is as follows: 1) the master sends a start condition. 2) the master sends the 7-bit slave id plus a write bit (low). 3) the addressed slave asserts an ack on the data line. 4) the master sends the 8-bit register address. 5) the slave asserts an ack on the data line only if the address is valid (nak if not). 6) the master sends 8 bits of data. 7) the slave asserts an ack on the data line. 8) repeat steps 6 and 7 as needed. 9) the master generates a stop condition. figure 22. write byte sequence figure 23. burst write sequence s p device slave address - w a 8 data bits from master to stave write single byte from slave to master a register address a s device slave address - w a 8 data bits - 1 burst write a register address a 8 data bits - n a 8 data bits - 2 a from master to stave from slave to master p
max14830 quad serial uart with 128-word fifos and internal oscillator 62 single-byte read with this operation the master sends an address and receives 1 or 2 data bytes from the slave device (figure 24). the read byte procedure is as follows: 1) the master sends a start condition. 2) the master sends the 7-bit slave id plus a write bit (low). 3) the addressed slave asserts an ack on the data line. 4) the master sends the 8-bit register address 5) the active slave asserts an ack on the data line only if the address is valid (nak if not). 6) the master sends a repeated start (sr). 7) the master sends the 7-bit slave id plus a read bit (high). 8) the addressed slave asserts an ack on the data line. 9) the slave sends 8 data bits. 10) the master asserts a nack on the data line. 11) the master generates a stop condition. burst read with this operation the master sends an address and receives multiple data bytes from the slave device (figure 25). the burst read procedure is as follows: 1) the master sends a start condition. 2) the master sends the 7-bit slave id plus a write bit (low). 3) the addressed slave asserts an ack on the data line. 4) the master sends the 8-bit register address. 5) the slave asserts an ack on the data line only if the address is valid (nak if not). 6) the master sends a repeated start condition. 7) the master sends the 7-bit slave id plus a read bit (high). 8) the slave asserts an ack on the data line. 9) the slave sends 8 bits of data. 10) the master asserts an ack on the data line. 11) repeat 9 and 10 as needed. 12) the master generates a stop condition. figure 24. read byte sequence figure 25. burst read sequence s sr device slave address - w a device slave address - r read single byte a register address a 8 data bits na from master to stave from slave to master p s sr device slave address - w a device slave address - r burst read a register address a 8 data bits - 1 a a 8 data bits - 3 8 data bits - 2 a 8 data bits - n a from master to stave from slave to master p
max14830 quad serial uart with 128-word fifos and internal oscillator 63 acknowledge bits data transfers are acknowledged with an acknowledge bit (ack) or a not-acknowledge bit (nack). both the master and the max14830 generate ack bits. to gener - ate an ack, pull sda low before the rising edge of the ninth clock pulse and keep it low during the high period of the ninth clock pulse (figure 26). to generate a nack, leave sda high before the rising edge of the ninth clock pulse and keep it high for the duration of the ninth clock pulse. monitoring for nack bits allows for detection of unsuccessful data transfers. applications information startup and initialization the max14830 is initialized following power-up or a hardware or software reset (figure 27). check that the max14830 is ready for operation after a power-up or reset by monitoring the irq output, if interrupt driven operation is employed. in polled mode, repeatedly read a known register until the expected contents are returned. low-power operation to reduce the power consumption during normal opera - tion, the following techniques can be adopted: ? do not use the internal pll. this saves the most power of the options listed here. disable and bypass the pll. ? use an external clock source. of the three clocking sources, the internal oscillator consumes the most power. the least amount of power is consumed when an external clock signal is used. ? use an external 1.8v supply at v 18 . this saves the power dissipated in the internal 1.8v linear regulator for the 1.8v core supply. disable the internal regulator by connecting ldoen to dgnd. ? keep internal clock rates as low as possible. ? use a low voltage on the v a supply. interrupts and polling monitor the max14830 by polling the isr register or by monitoring the irq output. in polled mode, the irq physical interrupt output is not used and the host control - ler polls the isr register at frequent intervals to establish the state of the max14830. alternatively, the physical interrupt, irq , of the max14830 can be used to interrupt the host controller at specified events, making polling unnecessary. the irq output is an open-drain output that requires a pullup resistor to v l . logic-level translation the max14830 can be directly connected to transceivers and controllers that have different supply voltages. the v l input defines the logic voltage levels of the control ler inter - face while the v ext voltage defines the logic of the trans - ceiver interface. this ensures flexibility when selecting a controller and transceiver. figure 28 is an example of a setup when the controller, transceiver, and the max14830 are powered by three different supplies. io-link application the typical operating circuit shows a four-part io-link master circuit with spi control on the max14830 and the io-link transceivers. figure 26. acknowledge bits figure 27. startup and initialization flow chart not acknowledge acknowledge 1 2 8 9 sda scl s power-up/ rst input pulled high configure clocking yes no configure fifo control configure flow control configure gpios start communication configure modes irq is high? or divlsb read successfully? enable interrupts
max14830 quad serial uart with 128-word fifos and internal oscillator 64 figure 28. logic-level translation figure 29. interchip synchronization 2.5v 3.3v 1.8v tx_ di ro de v l v a v cc v dd v ext rx_ dgnd agnd irq rst rts_ spi/i 2 c microcontroller transceiver max14830 max3078 gpio clktogpio gpio_ crystal oscillator xout xin crystalen pllen fractional baud-rate generator _ divider pll max14830 crystal oscillator xout xin fractional baud-rate generator _ crystalen pllen divider pll crystal oscillator xout xin crystalen fractional baud-rate generator _ phy8 phy9 phy10 phy11 phy4 phy5 phy6 phy7 phy0 phy1 phy2 phy3 divider pllen pll max14830 max14830
max14830 quad serial uart with 128-word fifos and internal oscillator 65 typical operating circuits port1 addr1 max14824 port2 addr2 rx txc max14824 txen port3 addr3 rx txc max14824 txen port4 addr4 rx txc max14824 txen rx txc txen v ext tx0 rx0 rtso mosi controller miso sclk rst cs2 cs1 rst cs sclk xin xout mosi miso tx1 rx1 rts1 gpio1 tx2 rx2 rts2 tx3 rx3 rts3 max14830 gpio5 gpio9 gpio13 io-link quad master application
max14830 quad serial uart with 128-word fifos and internal oscillator 66 typical operating circuits (continued) a0 di tx0 ldoen 0.1f 0.1f 3.3v v a v ext v l mosi miso sclk rx0 ro de b0 re max14840 a1 di ro de b1 re max14840 a2 di ro de b2 re max14840 a3 di ro de b3 re max14840 rts0 microcontroller tx0 mosi sclk irq ss tx1 rx1 rts1 tx2 rx2 rts2 tx3 rx3 rts3 dgnd agnd spi/i 2 c v 18 0.1f 0.1f irq cs quad rs-485 interface controlled through spi max14830
max14830 quad serial uart with 128-word fifos and internal oscillator 67 chip information process: bicmos package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 48 tqfn t4877+3 21-0144 90-0129
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 68 maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2010 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. max14830 quad serial uart with 128-word fifos and internal oscillator revision history revision number revision date description pages changed 0 9/10 initial release

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